Dynamic Simulation of a-IGZO TFT Circuits Using the Analytical Full Capacitance Model (AFCM)

• Main Authors: Y. Hernandez-Barrios, J. N. Gaspar-Angeles, M. Estrada, B. Iniguez, A. Cerdeira
• Format: Article
• Language: English
• Published: IEEE 2021-01-01
• Series: IEEE Journal of the Electron Devices Society
• Subjects: Circuit simulator; dynamic model; Verilog-A; capacitances model
• Online Access: https://ieeexplore.ieee.org/document/9296235/

The Analytical Full Capacitance Model (AFCM) for amorphous oxide semiconductors thin film transistors (AOSTFTs) is first validated, using a 19-stages Ring Oscillator (RO) fabricated and measured. The model was described in Verilog-A language to use it in a circuit simulator in this case SmartSpice from Silvaco. The model includes the extrinsic effects related to specific overlap capacitances present in bottom-gate AOSTFT structures. The dynamic behavior of the simulated circuit, when the TFT internal capacitances are increased or decreased and for different supply voltages of 10, 15 and 20 V, is compared with measured characteristics, obtaining a very good agreement. Afterwards, the AFCM is used to simulate the dynamic behavior of a pixel control circuit for a light emitting diode active matrix display (AMOLED), using an AOSTFT.