An FPGA-based cortical and thalamic silicon neuronal network

A DSSN model is a neuron model which is designed to be implemented efficiently by digital arithmetic circuit. In our previous study, we expanded this model to support the neuronal activities of several cortical and thalamic neurons; Regular spiking, fast spiking, intrinsically bursting and low-thres...

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Main Authors:	Takuya Nanami, Takashi Kohno
Format:	Article
Language:	English
Published:	Atlantis Press 2016-02-01
Series:	Journal of Robotics, Networking and Artificial Life (JRNAL)
Subjects:	silicon neuronal network neuron model FPGA cortex thalamus.
Online Access:	https://www.atlantis-press.com/article/25850511.pdf

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spelling	doaj-6fcc9687d81b456092440f81fa70d6c42020-11-24T22:00:49ZengAtlantis PressJournal of Robotics, Networking and Artificial Life (JRNAL)2352-63862016-02-012410.2991/jrnal.2016.2.4.8An FPGA-based cortical and thalamic silicon neuronal networkTakuya NanamiTakashi KohnoA DSSN model is a neuron model which is designed to be implemented efficiently by digital arithmetic circuit. In our previous study, we expanded this model to support the neuronal activities of several cortical and thalamic neurons; Regular spiking, fast spiking, intrinsically bursting and low-threshold spike. In this paper, we report our implementation of this expanded DSSN model and a kinetic-model-based silicon synapse on an FPGA device. Here, synaptic efficacy was stored in block RAMs, and external connection was realized based on a bus that conform to the address event representation. We simulated our circuit by the Xilinx Vivado design suit.https://www.atlantis-press.com/article/25850511.pdfsilicon neuronal networkneuron modelFPGAcortexthalamus.
collection	DOAJ
language	English
format	Article
sources	DOAJ
author	Takuya Nanami Takashi Kohno
spellingShingle	Takuya Nanami Takashi Kohno An FPGA-based cortical and thalamic silicon neuronal network Journal of Robotics, Networking and Artificial Life (JRNAL) silicon neuronal network neuron model FPGA cortex thalamus.
author_facet	Takuya Nanami Takashi Kohno
author_sort	Takuya Nanami
title	An FPGA-based cortical and thalamic silicon neuronal network
title_short	An FPGA-based cortical and thalamic silicon neuronal network
title_full	An FPGA-based cortical and thalamic silicon neuronal network
title_fullStr	An FPGA-based cortical and thalamic silicon neuronal network
title_full_unstemmed	An FPGA-based cortical and thalamic silicon neuronal network
title_sort	fpga-based cortical and thalamic silicon neuronal network
publisher	Atlantis Press
series	Journal of Robotics, Networking and Artificial Life (JRNAL)
issn	2352-6386
publishDate	2016-02-01
description	A DSSN model is a neuron model which is designed to be implemented efficiently by digital arithmetic circuit. In our previous study, we expanded this model to support the neuronal activities of several cortical and thalamic neurons; Regular spiking, fast spiking, intrinsically bursting and low-threshold spike. In this paper, we report our implementation of this expanded DSSN model and a kinetic-model-based silicon synapse on an FPGA device. Here, synaptic efficacy was stored in block RAMs, and external connection was realized based on a bus that conform to the address event representation. We simulated our circuit by the Xilinx Vivado design suit.
topic	silicon neuronal network neuron model FPGA cortex thalamus.
url	https://www.atlantis-press.com/article/25850511.pdf
work_keys_str_mv	AT takuyananami anfpgabasedcorticalandthalamicsiliconneuronalnetwork AT takashikohno anfpgabasedcorticalandthalamicsiliconneuronalnetwork AT takuyananami fpgabasedcorticalandthalamicsiliconneuronalnetwork AT takashikohno fpgabasedcorticalandthalamicsiliconneuronalnetwork
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An FPGA-based cortical and thalamic silicon neuronal network

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