The Area-Latency Symbiosis: Towards Improved Serial Encryption Circuits
The bit-sliding paper of Jean et al. (CHES 2017) showed that the smallest-size circuit for SPN based block ciphers such as AES, SKINNY and PRESENT can be achieved via bit-serial implementations. Their technique decreases the bit size of the datapath and naturally leads to a significant loss in late...
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Ruhr-Universität Bochum
2020-12-01
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doaj-706211e183f1486e96ca19c1c4464d172021-02-03T15:50:03ZengRuhr-Universität BochumTransactions on Cryptographic Hardware and Embedded Systems2569-29252020-12-0120211The Area-Latency Symbiosis: Towards Improved Serial Encryption CircuitsFatih Balli0Andrea Caforio1Subhadeep Banik2LASEC, École Polytechnique Fédérale de Lausanne, SwitzerlandLASEC, École Polytechnique Fédérale de Lausanne, SwitzerlandLASEC, École Polytechnique Fédérale de Lausanne, Switzerland The bit-sliding paper of Jean et al. (CHES 2017) showed that the smallest-size circuit for SPN based block ciphers such as AES, SKINNY and PRESENT can be achieved via bit-serial implementations. Their technique decreases the bit size of the datapath and naturally leads to a significant loss in latency (as well as the maximum throughput). Their designs complete a single round of the encryption in 168 (resp. 68) clock cycles for 128 (resp. 64) bit blocks. A follow-up work by Banik et al. (FSE 2020) introduced the swap-and-rotate technique that both eliminates this loss in latency and achieves even smaller footprints. In this paper, we extend these results on bit-serial implementations all the way to four authenticated encryption schemes from NIST LWC. Our first focus is to decrease latency and improve throughput with the use of the swap-and-rotate technique. Our block cipher implementations have the most efficient round operations in the sense that a round function of an n-bit block cipher is computed in exactly n clock cycles. This leads to implementations that are similar in size to the state of the art, but have much lower latency (savings up to 20 percent). We then extend our technique to 4- and 8-bit implementations. Although these results are promising, block ciphers themselves are not end-user primitives, as they need to be used in conjunction with a mode of operation. Hence, in the second part of the paper, we use our serial block ciphers to bootstrap four active NIST authenticated encryption candidates: SUNDAE-GIFT, Romulus, SAEAES and SKINNY-AEAD. In the wake of this effort, we provide the smallest block-cipher-based authenticated encryption circuits known in the literature so far. https://ojs-dev.ub.rub.de/index.php/TCHES/article/view/8734LightweightLatencySwapRotateBlock CipherAuthenticated Encryption |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Fatih Balli Andrea Caforio Subhadeep Banik |
spellingShingle |
Fatih Balli Andrea Caforio Subhadeep Banik The Area-Latency Symbiosis: Towards Improved Serial Encryption Circuits Transactions on Cryptographic Hardware and Embedded Systems Lightweight Latency Swap Rotate Block Cipher Authenticated Encryption |
author_facet |
Fatih Balli Andrea Caforio Subhadeep Banik |
author_sort |
Fatih Balli |
title |
The Area-Latency Symbiosis: Towards Improved Serial Encryption Circuits |
title_short |
The Area-Latency Symbiosis: Towards Improved Serial Encryption Circuits |
title_full |
The Area-Latency Symbiosis: Towards Improved Serial Encryption Circuits |
title_fullStr |
The Area-Latency Symbiosis: Towards Improved Serial Encryption Circuits |
title_full_unstemmed |
The Area-Latency Symbiosis: Towards Improved Serial Encryption Circuits |
title_sort |
area-latency symbiosis: towards improved serial encryption circuits |
publisher |
Ruhr-Universität Bochum |
series |
Transactions on Cryptographic Hardware and Embedded Systems |
issn |
2569-2925 |
publishDate |
2020-12-01 |
description |
The bit-sliding paper of Jean et al. (CHES 2017) showed that the smallest-size circuit for SPN based block ciphers such as AES, SKINNY and PRESENT can be achieved via bit-serial implementations. Their technique decreases the bit size of the datapath and naturally leads to a significant loss in latency (as well as the maximum throughput). Their designs complete a single round of the encryption in 168 (resp. 68) clock cycles for 128 (resp. 64) bit blocks. A follow-up work by Banik et al. (FSE 2020) introduced the swap-and-rotate technique that both eliminates this loss in latency and achieves even smaller footprints.
In this paper, we extend these results on bit-serial implementations all the way to four authenticated encryption schemes from NIST LWC. Our first focus is to decrease latency and improve throughput with the use of the swap-and-rotate technique. Our block cipher implementations have the most efficient round operations in the sense that a round function of an n-bit block cipher is computed in exactly n clock cycles. This leads to implementations that are similar in size to the state of the art, but have much lower latency (savings up to 20 percent). We then extend our technique to 4- and 8-bit implementations. Although these results are promising, block ciphers themselves are not end-user primitives, as they need to be used in conjunction with a mode of operation. Hence, in the second part of the paper, we use our serial block ciphers to bootstrap four active NIST authenticated encryption candidates: SUNDAE-GIFT, Romulus, SAEAES and SKINNY-AEAD. In the wake of this effort, we provide the smallest block-cipher-based authenticated encryption circuits known in the literature so far.
|
topic |
Lightweight Latency Swap Rotate Block Cipher Authenticated Encryption |
url |
https://ojs-dev.ub.rub.de/index.php/TCHES/article/view/8734 |
work_keys_str_mv |
AT fatihballi thearealatencysymbiosistowardsimprovedserialencryptioncircuits AT andreacaforio thearealatencysymbiosistowardsimprovedserialencryptioncircuits AT subhadeepbanik thearealatencysymbiosistowardsimprovedserialencryptioncircuits AT fatihballi arealatencysymbiosistowardsimprovedserialencryptioncircuits AT andreacaforio arealatencysymbiosistowardsimprovedserialencryptioncircuits AT subhadeepbanik arealatencysymbiosistowardsimprovedserialencryptioncircuits |
_version_ |
1724286516585299968 |