FPGA Implementation of L<sub>1/2</sub> Sparsity Constrained Nonnegative Matrix Factorization Algorithm for Remotely Sensed Hyperspectral Image Analysis

Remotely sensed hyperspectral images provide data of the earth's surface components. The data provided is collected through airborne devices such as satellites with the capability to collect large amounts of data to be sent to ground stations for processing. The main disadvantage of this scenar...

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Bibliographic Details
Main Authors: Mostafa Guda, Safa Gasser, Mohamed S. El-Mahallawy, Khaled Shehata
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Access
Subjects:
Online Access:https://ieeexplore.ieee.org/document/8957084/
Description
Summary:Remotely sensed hyperspectral images provide data of the earth's surface components. The data provided is collected through airborne devices such as satellites with the capability to collect large amounts of data to be sent to ground stations for processing. The main disadvantage of this scenario is the limited bandwidth connection between the airborne devices and the ground station on Earth which affects the information sending and real time processing. A possible solution is to include an on-board data processor. Field-Programmable Gate Arrays (FPGAs) are excellent target platform that allows the design reconfigurability, powerful computing and high performance levels. One of the most commonly used techniques in hyperspectral data analysis is linear spectral unmixing. In the last decade, L&#x221A; sparsity constrained Nonnegative Matrix Factorization (NMF), a linear spectral unmixing algorithm, and its extensions have been heavily studied to unmix the hyperspectral images and recover their material spectra. L<sub>1/2</sub> regularizer is proven to have much better results in terms of sparsity and accuracy than other regularizers yet, to the best of our knowledge, has not been implemented. In this paper, we present an FPGA design for the L<sub>1/2</sub> sparsity constrained NMF (L<sub>1/2</sub>-NMF) algorithm. The proposed design is tested on both synthetic and real data sets and implemented on Altera Family FPGAs. Implementation results show that the proposed design successfully unmixes the data with maximum frequency of 52.6 MHz and a speedup factor of 3.9 for the synthetic data set and a frequency of 104.32 MHz and a speedup factor of 1.14 for the real data set. The implementation results are compared to the simulation results and ground truth signatures using Spectral Angular Distance (SAD) measure. Calculations show that the implementation results have comparable SAD values to the simulation results.
ISSN:2169-3536