Optimization design of binary VGG convolutional neural network accelerator

Optimization design of binary VGG convolutional neural network accelerator

Most of the existing researches on accelerators of binary convolutional neural networks based on FPGA are aimed at small-scale image input, while the applications mainly take large-scale convolutional neural networks such as YOLO and VGG as backbone networks. The hardware of convolutional neural net...

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Bibliographic Details
Main Authors: Zhang Xuxin, Zhang Jia, Li Xinzeng, Jin Jie
Format: Article
Language:zho
Published: National Computer System Engineering Research Institute of China 2021-02-01
Series:Dianzi Jishu Yingyong
Subjects:
optimization design
binary convolutional neural network
fpga accelerator
Online Access:http://www.chinaaet.com/article/3000128918
Description
Summary:Most of the existing researches on accelerators of binary convolutional neural networks based on FPGA are aimed at small-scale image input, while the applications mainly take large-scale convolutional neural networks such as YOLO and VGG as backbone networks. The hardware of convolutional neural network is optimized and designed from the two aspects including the network topology and pipeline stage, so as to solve the bottleneck of logic resources and improve the performance of the binary VGG network accelerator. CIFAR-10 dataset resized to 224×224 was used to verify the optimized design of VGG convolutional neural network accelerator based on FPGA. Experimental results showed that the system achieved 81% recognition accuracy and 219.9 FPS recognition speed，which verified the effectiveness of the optimization method.
ISSN:0258-7998

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