Optimization design of binary VGG convolutional neural network accelerator

Optimization design of binary VGG convolutional neural network accelerator

Most of the existing researches on accelerators of binary convolutional neural networks based on FPGA are aimed at small-scale image input, while the applications mainly take large-scale convolutional neural networks such as YOLO and VGG as backbone networks. The hardware of convolutional neural net...

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Bibliographic Details
Main Authors: Zhang Xuxin, Zhang Jia, Li Xinzeng, Jin Jie
Format: Article
Language:zho
Published: National Computer System Engineering Research Institute of China 2021-02-01
Series:Dianzi Jishu Yingyong
Subjects:
optimization design
binary convolutional neural network
fpga accelerator
Online Access:http://www.chinaaet.com/article/3000128918
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spelling doaj-765696937da34157b9a0d203378aa9032021-05-21T05:34:34ZzhoNational Computer System Engineering Research Institute of ChinaDianzi Jishu Yingyong0258-79982021-02-01472202310.16157/j.issn.0258-7998.2012073000128918Optimization design of binary VGG convolutional neural network acceleratorZhang Xuxin0Zhang Jia1Li Xinzeng2Jin Jie3College of Electronic and Electrical Engineering，Shanghai University of Engineering Science，Shanghai 201600，ChinaCollege of Electronic and Electrical Engineering，Shanghai University of Engineering Science，Shanghai 201600，ChinaCollege of Electronic and Electrical Engineering，Shanghai University of Engineering Science，Shanghai 201600，ChinaCollege of Electronic and Electrical Engineering，Shanghai University of Engineering Science，Shanghai 201600，ChinaMost of the existing researches on accelerators of binary convolutional neural networks based on FPGA are aimed at small-scale image input, while the applications mainly take large-scale convolutional neural networks such as YOLO and VGG as backbone networks. The hardware of convolutional neural network is optimized and designed from the two aspects including the network topology and pipeline stage, so as to solve the bottleneck of logic resources and improve the performance of the binary VGG network accelerator. CIFAR-10 dataset resized to 224×224 was used to verify the optimized design of VGG convolutional neural network accelerator based on FPGA. Experimental results showed that the system achieved 81% recognition accuracy and 219.9 FPS recognition speed，which verified the effectiveness of the optimization method.http://www.chinaaet.com/article/3000128918optimization designbinary convolutional neural networkfpga accelerator
collection DOAJ
language zho
format Article
sources DOAJ
author Zhang Xuxin
Zhang Jia
Li Xinzeng
Jin Jie
spellingShingle Zhang Xuxin
Zhang Jia
Li Xinzeng
Jin Jie
Optimization design of binary VGG convolutional neural network accelerator
Dianzi Jishu Yingyong
optimization design
binary convolutional neural network
fpga accelerator
author_facet Zhang Xuxin
Zhang Jia
Li Xinzeng
Jin Jie
author_sort Zhang Xuxin
title Optimization design of binary VGG convolutional neural network accelerator
title_short Optimization design of binary VGG convolutional neural network accelerator
title_full Optimization design of binary VGG convolutional neural network accelerator
title_fullStr Optimization design of binary VGG convolutional neural network accelerator
title_full_unstemmed Optimization design of binary VGG convolutional neural network accelerator
title_sort optimization design of binary vgg convolutional neural network accelerator
publisher National Computer System Engineering Research Institute of China
series Dianzi Jishu Yingyong
issn 0258-7998
publishDate 2021-02-01
description Most of the existing researches on accelerators of binary convolutional neural networks based on FPGA are aimed at small-scale image input, while the applications mainly take large-scale convolutional neural networks such as YOLO and VGG as backbone networks. The hardware of convolutional neural network is optimized and designed from the two aspects including the network topology and pipeline stage, so as to solve the bottleneck of logic resources and improve the performance of the binary VGG network accelerator. CIFAR-10 dataset resized to 224×224 was used to verify the optimized design of VGG convolutional neural network accelerator based on FPGA. Experimental results showed that the system achieved 81% recognition accuracy and 219.9 FPS recognition speed，which verified the effectiveness of the optimization method.
topic optimization design
binary convolutional neural network
fpga accelerator
url http://www.chinaaet.com/article/3000128918
work_keys_str_mv AT zhangxuxin optimizationdesignofbinaryvggconvolutionalneuralnetworkaccelerator
AT zhangjia optimizationdesignofbinaryvggconvolutionalneuralnetworkaccelerator
AT lixinzeng optimizationdesignofbinaryvggconvolutionalneuralnetworkaccelerator
AT jinjie optimizationdesignofbinaryvggconvolutionalneuralnetworkaccelerator
_version_ 1721432441152864256

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