Separating VNF and Network Control for Hardware‐Acceleration of SDN/NFV Architecture

• Main Authors: Tong Duan, Julong Lan, Yuxiang Hu, Penghao Sun
• Format: Article
• Language: English
• Published: Electronics and Telecommunications Research Institute (ETRI) 2017-08-01
• Series: ETRI Journal
• Subjects: NFV; SDN; Hardware‐acceleration; Network function chaining; NetFPGA
• Online Access: https://doi.org/10.4218/etrij.17.0117.0174

A hardware‐acceleration architecture that separates virtual network functions (VNFs) and network control (called HSN) is proposed to solve the mismatch between the simple flow steering requirements and strong packet processing abilities of software‐defined networking (SDN) forwarding elements (FEs) in SDN/network function virtualization (NFV) architecture, while improving the efficiency of NFV infrastructure and the performance of network‐intensive functions. HSN makes full use of FEs and accelerates VNFs through two mechanisms: (1) separation of traffic steering and packet processing in the FEs; (2) separation of SDN and NFV control in the FEs. Our HSN prototype, built on NetFPGA‐10G, demonstrates that the processing performance can be greatly improved with only a small modification of the traditional SDN/NFV architecture.