Automatic Configurable Hardware Code Generation for Software-Defined Radios
The development of software-defined radio (SDR) systems using field-programmable gate arrays (FPGAs) compels designers to reuse pre-existing Intellectual Property (IP) cores in order to meet time-to-market and design efficiency requirements. However, the low-level development difficulties associated...
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doaj-8107985ddc5b4a2684a04b15a6e7e59c2020-11-25T00:54:56ZengMDPI AGComputers2073-431X2018-10-01745310.3390/computers7040053computers7040053Automatic Configurable Hardware Code Generation for Software-Defined RadiosLekhobola Tsoeunyane0Simon Winberg1Michael Inggs2Software Defined Radio Group, Electrical Engineering Department, University of Cape Town, Cape Town 7701, South AfricaSoftware Defined Radio Group, Electrical Engineering Department, University of Cape Town, Cape Town 7701, South AfricaSoftware Defined Radio Group, Electrical Engineering Department, University of Cape Town, Cape Town 7701, South AfricaThe development of software-defined radio (SDR) systems using field-programmable gate arrays (FPGAs) compels designers to reuse pre-existing Intellectual Property (IP) cores in order to meet time-to-market and design efficiency requirements. However, the low-level development difficulties associated with FPGAs hinder productivity, even when the designer is experienced with hardware design. These low-level difficulties include non-standard interfacing methods, component communication and synchronization challenges, complicated timing constraints and processing blocks that need to be customized through time-consuming design tweaks. In this paper, we present a methodology for automated and behavioral integration of dedicated IP cores for rapid prototyping of SDR applications. To maintain high performance of the SDR designs, our methodology integrates IP cores using characteristics of the dataflow model of computation (MoC), namely the static dataflow with access patterns (SDF-AP). We show how the dataflow is mapped onto the low-level model of hardware by efficiently applying low-level based optimizations and using a formal analysis technique that guarantees the correctness of the generated solutions. Furthermore, we demonstrate the capability of our automated hardware design approach by developing eight SDR applications in VHDL. The results show that well-optimized designs are generated and that this can improve productivity while also conserving the hardware resources used.http://www.mdpi.com/2073-431X/7/4/53reconfigurable computingfield programmable technologiesfield programmable gate arraysFPGAsdesign automationsoftware-defined radiodomain-specific languagehigh-level synthesis |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Lekhobola Tsoeunyane Simon Winberg Michael Inggs |
spellingShingle |
Lekhobola Tsoeunyane Simon Winberg Michael Inggs Automatic Configurable Hardware Code Generation for Software-Defined Radios Computers reconfigurable computing field programmable technologies field programmable gate arrays FPGAs design automation software-defined radio domain-specific language high-level synthesis |
author_facet |
Lekhobola Tsoeunyane Simon Winberg Michael Inggs |
author_sort |
Lekhobola Tsoeunyane |
title |
Automatic Configurable Hardware Code Generation for Software-Defined Radios |
title_short |
Automatic Configurable Hardware Code Generation for Software-Defined Radios |
title_full |
Automatic Configurable Hardware Code Generation for Software-Defined Radios |
title_fullStr |
Automatic Configurable Hardware Code Generation for Software-Defined Radios |
title_full_unstemmed |
Automatic Configurable Hardware Code Generation for Software-Defined Radios |
title_sort |
automatic configurable hardware code generation for software-defined radios |
publisher |
MDPI AG |
series |
Computers |
issn |
2073-431X |
publishDate |
2018-10-01 |
description |
The development of software-defined radio (SDR) systems using field-programmable gate arrays (FPGAs) compels designers to reuse pre-existing Intellectual Property (IP) cores in order to meet time-to-market and design efficiency requirements. However, the low-level development difficulties associated with FPGAs hinder productivity, even when the designer is experienced with hardware design. These low-level difficulties include non-standard interfacing methods, component communication and synchronization challenges, complicated timing constraints and processing blocks that need to be customized through time-consuming design tweaks. In this paper, we present a methodology for automated and behavioral integration of dedicated IP cores for rapid prototyping of SDR applications. To maintain high performance of the SDR designs, our methodology integrates IP cores using characteristics of the dataflow model of computation (MoC), namely the static dataflow with access patterns (SDF-AP). We show how the dataflow is mapped onto the low-level model of hardware by efficiently applying low-level based optimizations and using a formal analysis technique that guarantees the correctness of the generated solutions. Furthermore, we demonstrate the capability of our automated hardware design approach by developing eight SDR applications in VHDL. The results show that well-optimized designs are generated and that this can improve productivity while also conserving the hardware resources used. |
topic |
reconfigurable computing field programmable technologies field programmable gate arrays FPGAs design automation software-defined radio domain-specific language high-level synthesis |
url |
http://www.mdpi.com/2073-431X/7/4/53 |
work_keys_str_mv |
AT lekhobolatsoeunyane automaticconfigurablehardwarecodegenerationforsoftwaredefinedradios AT simonwinberg automaticconfigurablehardwarecodegenerationforsoftwaredefinedradios AT michaelinggs automaticconfigurablehardwarecodegenerationforsoftwaredefinedradios |
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1725232682046062592 |