A Fast Approach for Generating Efficient Parsers on FPGAs

• Main Authors: Zhuang Cao, Huiguo Zhang, Junnan Li, Mei Wen, Chunyuan Zhang
• Format: Article
• Language: English
• Published: MDPI AG 2019-10-01
• Series: Symmetry
• Subjects: packet parser; pipeline; p4; fpga
• Online Access: https://www.mdpi.com/2073-8994/11/10/1265

The development of modern networking requires that high-performance network processors be designed quickly and efficiently to support new protocols. As a very important part of the processor, the parser parses the headers of the packets—this is the precondition for further processing and finally forwarding these packets. This paper presents a framework designed to transform P4 programs to VHDL and to generate parsers on Field Programmable Gate Arrays (FPGAs). The framework includes a pipeline-based hardware architecture and a back-end compiler. The hardware architecture comprises many components with varying functionality, each of which has its own optimized VHDL template. By using the output of a standard frontend P4 compiler, our proposed compiler extracts the parameters and relationships from within the used components, which can then be mapped to corresponding templates by configuring, optimizing, and instantiating them. Finally, these templates are connected to output VHDL code. When a prototype of this framework is implemented and evaluated, the results demonstrate that the throughputs of the generated parsers achieve nearly 320 Gbps at a clock rate of around 300 MHz. Compared with state-of-the-art solutions, our proposed parsers achieve an average of twice the throughput when similar amounts of resources are being used.