Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates

Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates

A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suff...

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Bibliographic Details
Main Authors: Tung-Yu Liu, Fu-Ming Pan, Jeng-Tzong Sheu
Format: Article
Language:English
Published: IEEE 2015-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
Gate-all-around (GAA)
poly-Si
junctionless (JL)
nanowire (NW)
sidewall spacer
transistor
Online Access:https://ieeexplore.ieee.org/document/7118129/
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spelling doaj-82cbcf2b246d402389cabae255c718362021-03-29T18:43:26ZengIEEEIEEE Journal of the Electron Devices Society2168-67342015-01-013540540910.1109/JEDS.2015.24417367118129Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm GatesTung-Yu Liu0Fu-Ming Pan1Jeng-Tzong Sheu2Institute of Nanotechnology/Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu, TaiwanInstitute of Nanotechnology/Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu, TaiwanInstitute of Nanotechnology/Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu, TaiwanA high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high I<sub>on</sub>/I<sub>off</sub> current ratio of 7 &#x00D7; 10<sup>8</sup> (VG = 4 V and V<sub>D</sub> = 1 V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.https://ieeexplore.ieee.org/document/7118129/Gate-all-around (GAA)poly-Sijunctionless (JL)nanowire (NW)sidewall spacertransistor
collection DOAJ
language English
format Article
sources DOAJ
author Tung-Yu Liu
Fu-Ming Pan
Jeng-Tzong Sheu
spellingShingle Tung-Yu Liu
Fu-Ming Pan
Jeng-Tzong Sheu
Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates
IEEE Journal of the Electron Devices Society
Gate-all-around (GAA)
poly-Si
junctionless (JL)
nanowire (NW)
sidewall spacer
transistor
author_facet Tung-Yu Liu
Fu-Ming Pan
Jeng-Tzong Sheu
author_sort Tung-Yu Liu
title Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates
title_short Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates
title_full Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates
title_fullStr Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates
title_full_unstemmed Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates
title_sort characteristics of gate-all-around junctionless polysilicon nanowire transistors with twin 20-nm gates
publisher IEEE
series IEEE Journal of the Electron Devices Society
issn 2168-6734
publishDate 2015-01-01
description A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high I<sub>on</sub>/I<sub>off</sub> current ratio of 7 &#x00D7; 10<sup>8</sup> (VG = 4 V and V<sub>D</sub> = 1 V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.
topic Gate-all-around (GAA)
poly-Si
junctionless (JL)
nanowire (NW)
sidewall spacer
transistor
url https://ieeexplore.ieee.org/document/7118129/
work_keys_str_mv AT tungyuliu characteristicsofgateallaroundjunctionlesspolysiliconnanowiretransistorswithtwin20nmgates
AT fumingpan characteristicsofgateallaroundjunctionlesspolysiliconnanowiretransistorswithtwin20nmgates
AT jengtzongsheu characteristicsofgateallaroundjunctionlesspolysiliconnanowiretransistorswithtwin20nmgates
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