Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS

Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS

In this paper, very compact, standard cell-based Digital-to-Analog converters (DACs) based on the Dyadic Digital Pulse Modulation (DDPM) are presented. As fundamental contribution, an optimal sampling condition is analytically derived to enhance DDPM conversion with inherent suppression of spurious...

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Bibliographic Details
Main Authors: Orazio Aiello, Paolo Crovetti, Massimo Alioto
Format: Article
Language:English
Published: IEEE 2019-01-01
Series:IEEE Access
Subjects:
Digital to analog converter (DAC)
automated design
calibration
fully synthesizable
fully digital
ultra-low design effort
Online Access:https://ieeexplore.ieee.org/document/8821285/
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spelling doaj-8bcd8577ff01455cbb6d9a4967e7019d2021-03-29T23:20:45ZengIEEEIEEE Access2169-35362019-01-01712647912648810.1109/ACCESS.2019.29387378821285Standard Cell-Based Ultra-Compact DACs in 40-nm CMOSOrazio Aiello0https://orcid.org/0000-0002-6938-9806Paolo Crovetti1Massimo Alioto2Department of Electronics and Telecommunications (DET), Politecnico di Torino, Turin, ItalyDepartment of Electronics and Telecommunications (DET), Politecnico di Torino, Turin, ItalyDepartment of Electrical and Computer Engineering, National University of Singapore, SingaporeIn this paper, very compact, standard cell-based Digital-to-Analog converters (DACs) based on the Dyadic Digital Pulse Modulation (DDPM) are presented. As fundamental contribution, an optimal sampling condition is analytically derived to enhance DDPM conversion with inherent suppression of spurious harmonics. Operation under such optimal condition is experimentally demonstrated to assure resolution up to 16 bits, with 9.4-239X area reduction compared to prior art. The digital nature of the circuits also allows extremely low design effort in the order of 10 man-hours, portability across CMOS generations, and operation at the lowest supply voltage reported to date. The limitations of DDPM converters, the benefits of the optimal sampling condition and digital calibration were explored through the optimized design and the experimental characterization of two DACs with moderate and high resolution. The first is a general-purpose DAC for baseband signals achieving 12-bit (11.6 ENOB) resolution at 110kS/s sample rate and consuming 50.8&#x03BC;W, the second is a DAC for DC calibration achieving 16-bit resolution with 3.1-LSB INL, 2.5-LSB DNL, 45&#x03BC;W power, at only 530&#x03BC;m<sup>2</sup> area.https://ieeexplore.ieee.org/document/8821285/Digital to analog converter (DAC)automated designcalibrationfully synthesizablefully digitalultra-low design effort
collection DOAJ
language English
format Article
sources DOAJ
author Orazio Aiello
Paolo Crovetti
Massimo Alioto
spellingShingle Orazio Aiello
Paolo Crovetti
Massimo Alioto
Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS
IEEE Access
Digital to analog converter (DAC)
automated design
calibration
fully synthesizable
fully digital
ultra-low design effort
author_facet Orazio Aiello
Paolo Crovetti
Massimo Alioto
author_sort Orazio Aiello
title Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS
title_short Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS
title_full Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS
title_fullStr Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS
title_full_unstemmed Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS
title_sort standard cell-based ultra-compact dacs in 40-nm cmos
publisher IEEE
series IEEE Access
issn 2169-3536
publishDate 2019-01-01
description In this paper, very compact, standard cell-based Digital-to-Analog converters (DACs) based on the Dyadic Digital Pulse Modulation (DDPM) are presented. As fundamental contribution, an optimal sampling condition is analytically derived to enhance DDPM conversion with inherent suppression of spurious harmonics. Operation under such optimal condition is experimentally demonstrated to assure resolution up to 16 bits, with 9.4-239X area reduction compared to prior art. The digital nature of the circuits also allows extremely low design effort in the order of 10 man-hours, portability across CMOS generations, and operation at the lowest supply voltage reported to date. The limitations of DDPM converters, the benefits of the optimal sampling condition and digital calibration were explored through the optimized design and the experimental characterization of two DACs with moderate and high resolution. The first is a general-purpose DAC for baseband signals achieving 12-bit (11.6 ENOB) resolution at 110kS/s sample rate and consuming 50.8&#x03BC;W, the second is a DAC for DC calibration achieving 16-bit resolution with 3.1-LSB INL, 2.5-LSB DNL, 45&#x03BC;W power, at only 530&#x03BC;m<sup>2</sup> area.
topic Digital to analog converter (DAC)
automated design
calibration
fully synthesizable
fully digital
ultra-low design effort
url https://ieeexplore.ieee.org/document/8821285/
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AT paolocrovetti standardcellbasedultracompactdacsin40nmcmos
AT massimoalioto standardcellbasedultracompactdacsin40nmcmos
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