An Innovative Successive Approximation Register Analog-to-Digital Converter for a Nine-Axis Sensing System

• Main Authors: Chih-Hsuan Lin, Kuei-Ann Wen
• Format: Article
• Language: English
• Published: MDPI AG 2021-01-01
• Series: Journal of Low Power Electronics and Applications
• Subjects: reconfigurable; SAR-ADC; fine (3 MSBs) plus course conversion (11 LSBs) CDAC; DFT-based
• Online Access: https://www.mdpi.com/2079-9268/11/1/3

With nine-axis sensing systems in 5G smartphones, mobile power consumption has become increasingly important, and ultra-low-power (ULP) sensor circuits can decrease power consumption to tens of microwatts. This paper presents an innovative successive approximation register analog-to-digital converter, which comprises fine (three most significant bits (MSBs) plus course conversion (11 least significant bits (LSBs)) capacitive digital-to-analog converters (CDACs), ULP, four-mode reconfigurable resolution (9, 10, 11, or 12 bits), an internally generated clock, meta-detection, the switching base midpoint voltage (Vm) (SW-B-M), bit control logic, multi-phase control logic, fine (three MSBs) plus course conversion (11 LSBs) switch control logic, phase control logic, and an input signal plus negative voltage (VI + NEG) voltage generator. Then, the mechanism of the discrete Fourier transform (DFT)-based calibration is applied. The scalable voltage technique was used, and the analog/digital voltage was <i>V_analog</i> (1.5 V) and <i>V_digital</i> (0.9 V) to meet the specifications of the nine-axis ULP sensing system. The CDACs can reconfigure four-mode resolutions, 9–12 bits, for use in nine-axis sensor applications. The corresponding dynamic signal-to-noise and distortion ratio performance was 50.78, 58.53, 62.42, and 66.51 dB. In the 12-bit mode, the power consumption of the ADC was approximately 2.7 μW, and the corresponding figure of merit (FoM) was approximately 30.5 fJ for each conversion step.