FPGA-Based Multi-Level Approximate Multipliers for High-Performance Error-Resilient Applications
This paper presents approximate multipliers which are efficiently deployed on Field Programmable Gate Arrays (FPGAs) by using newly proposed approximate logic compressors at different levels of accuracy. Our approximate multiplier designs offer higher gains of power-delay-area products (PDAP) than t...
Main Authors: | Nguyen Van Toan, Jeong-Gun Lee |
---|---|
Format: | Article |
Language: | English |
Published: |
IEEE
2020-01-01
|
Series: | IEEE Access |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/8978722/ |
Similar Items
-
Approximate Multiplier Design Using Novel Dual-Stage 4:2 Compressors
by: Pranose J. Edavoor, et al.
Published: (2020-01-01) -
Design and Analysis of Multiplier Using Approximate 15-4 Compressor
by: R. Marimuthu, et al.
Published: (2017-01-01) -
CNN Inference Using a Preprocessing Precision Controller and Approximate Multipliers With Various Precisions
by: Issam Hammad, et al.
Published: (2021-01-01) -
Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors
by: Roberto R. Osorio, et al.
Published: (2019-01-01) -
Approximate Array Multipliers
by: Padmanabhan Balasubramanian, et al.
Published: (2021-03-01)