Ramesh, S. R., & Jayaparvathy, R. (2019). Artificial neural network model for arrival time computation in gate level circuits. Taylor & Francis Group.
Chicago Style (17th ed.) CitationRamesh, S. R., and R. Jayaparvathy. Artificial Neural Network Model for Arrival Time Computation in Gate Level Circuits. Taylor & Francis Group, 2019.
MLA (8th ed.) CitationRamesh, S. R., and R. Jayaparvathy. Artificial Neural Network Model for Arrival Time Computation in Gate Level Circuits. Taylor & Francis Group, 2019.
Warning: These citations may not always be 100% accurate.