Artificial neural network model for arrival time computation in gate level circuits
Advances in the VLSI process technology lead to variations in the process parameters. These process variations severely affect the delay computation of a digital circuit. Under such variations, the various delays, i.e. net delay, gate delay, etc., are no longer deterministic. They are random in natu...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Taylor & Francis Group
2019-07-01
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| Series: | Automatika |
| Subjects: | |
| Online Access: | http://dx.doi.org/10.1080/00051144.2019.1631568 |