Dual Super-Systolic Core for Real-Time Reconstructive Algorithms of High-Resolution Radar/SAR Imaging Systems
A high-speed dual super-systolic core for reconstructive signal processing (SP) operations consists of a double parallel systolic array (SA) machine in which each processing element of the array is also conceptualized as another SA in a bit-level fashion. In this study, we addressed the design of a...
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Online Access: | http://www.mdpi.com/1424-8220/12/3/2539/ |
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doaj-a2b3769f3a7c490cb68973b2cb299ee12020-11-25T00:09:33ZengMDPI AGSensors1424-82202012-02-011232539256010.3390/s120302539Dual Super-Systolic Core for Real-Time Reconstructive Algorithms of High-Resolution Radar/SAR Imaging SystemsJavier Vázquez CastilloAlejandro Castillo AtocheA high-speed dual super-systolic core for reconstructive signal processing (SP) operations consists of a double parallel systolic array (SA) machine in which each processing element of the array is also conceptualized as another SA in a bit-level fashion. In this study, we addressed the design of a high-speed dual super-systolic array (SSA) core for the enhancement/reconstruction of remote sensing (RS) imaging of radar/synthetic aperture radar (SAR) sensor systems. The selected reconstructive SP algorithms are efficiently transformed in their parallel representation and then, they are mapped into an efficient high performance embedded computing (HPEC) architecture in reconfigurable Xilinx field programmable gate array (FPGA) platforms. As an implementation test case, the proposed approach was aggregated in a HW/SW co-design scheme in order to solve the nonlinear ill-posed inverse problem of nonparametric estimation of the power spatial spectrum pattern (SSP) from a remotely sensed scene. We show how such dual SSA core, drastically reduces the computational load of complex RS regularization techniques achieving the required real-time operational mode.http://www.mdpi.com/1424-8220/12/3/2539/super-systolicparallel computingremote sensingFPGA |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Javier Vázquez Castillo Alejandro Castillo Atoche |
spellingShingle |
Javier Vázquez Castillo Alejandro Castillo Atoche Dual Super-Systolic Core for Real-Time Reconstructive Algorithms of High-Resolution Radar/SAR Imaging Systems Sensors super-systolic parallel computing remote sensing FPGA |
author_facet |
Javier Vázquez Castillo Alejandro Castillo Atoche |
author_sort |
Javier Vázquez Castillo |
title |
Dual Super-Systolic Core for Real-Time Reconstructive Algorithms of High-Resolution Radar/SAR Imaging Systems |
title_short |
Dual Super-Systolic Core for Real-Time Reconstructive Algorithms of High-Resolution Radar/SAR Imaging Systems |
title_full |
Dual Super-Systolic Core for Real-Time Reconstructive Algorithms of High-Resolution Radar/SAR Imaging Systems |
title_fullStr |
Dual Super-Systolic Core for Real-Time Reconstructive Algorithms of High-Resolution Radar/SAR Imaging Systems |
title_full_unstemmed |
Dual Super-Systolic Core for Real-Time Reconstructive Algorithms of High-Resolution Radar/SAR Imaging Systems |
title_sort |
dual super-systolic core for real-time reconstructive algorithms of high-resolution radar/sar imaging systems |
publisher |
MDPI AG |
series |
Sensors |
issn |
1424-8220 |
publishDate |
2012-02-01 |
description |
A high-speed dual super-systolic core for reconstructive signal processing (SP) operations consists of a double parallel systolic array (SA) machine in which each processing element of the array is also conceptualized as another SA in a bit-level fashion. In this study, we addressed the design of a high-speed dual super-systolic array (SSA) core for the enhancement/reconstruction of remote sensing (RS) imaging of radar/synthetic aperture radar (SAR) sensor systems. The selected reconstructive SP algorithms are efficiently transformed in their parallel representation and then, they are mapped into an efficient high performance embedded computing (HPEC) architecture in reconfigurable Xilinx field programmable gate array (FPGA) platforms. As an implementation test case, the proposed approach was aggregated in a HW/SW co-design scheme in order to solve the nonlinear ill-posed inverse problem of nonparametric estimation of the power spatial spectrum pattern (SSP) from a remotely sensed scene. We show how such dual SSA core, drastically reduces the computational load of complex RS regularization techniques achieving the required real-time operational mode. |
topic |
super-systolic parallel computing remote sensing FPGA |
url |
http://www.mdpi.com/1424-8220/12/3/2539/ |
work_keys_str_mv |
AT javiervazquezcastillo dualsupersystoliccoreforrealtimereconstructivealgorithmsofhighresolutionradarsarimagingsystems AT alejandrocastilloatoche dualsupersystoliccoreforrealtimereconstructivealgorithmsofhighresolutionradarsarimagingsystems |
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1725411378812944384 |