An Approach to the Construction of a Network Processing Unit

The paper proposes the architecture and basic requirements for a network processor for OpenFlow switches of software-defined networks. An analysis of the architectures of well-known network processors is presented − NP-5 from EZchip (now Mellanox) and Tofino from Barefoot Networks. The advantages an...

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Bibliographic Details
Main Authors: Stanislav O. Bezzubtsev, Vyacheslav V. Vasin, Dmitry Yu. Volkanov, Shynar R. Zhailauova, Vladislav A. Miroshnik, Yuliya A. Skobtsova, Ruslan L. Smeliansky
Format: Article
Language:English
Published: Yaroslavl State University 2019-03-01
Series:Modelirovanie i Analiz Informacionnyh Sistem
Subjects:
sdn
Online Access:https://www.mais-journal.ru/jour/article/view/1161
Description
Summary:The paper proposes the architecture and basic requirements for a network processor for OpenFlow switches of software-defined networks. An analysis of the architectures of well-known network processors is presented − NP-5 from EZchip (now Mellanox) and Tofino from Barefoot Networks. The advantages and disadvantages of two different versions of network processor architectures are considered: pipeline-based architecture, the stages of which are represented by a set of general-purpose processor cores, and pipeline-based architecture whose stages correspond to cores specialized for specific packet processing operations. Based on a dedicated set of the most common use case scenarios, a new architecture of the network processor unit (NPU) with functionally specialized pipeline stages was proposed. The article presents a description of the simulation model of the NPU of the proposed architecture. The simulation model of the network processor is implemented in C ++ languages using SystemC, the open-source C++ library. For the functional testing of the obtained NPU model, the described use case scenarios were implemented in C. In order to evaluate the performance of the proposed NPU architecture a set of software products developed by KM211 company and the KMX32 family of microcontrollers were used. Evaluation of NPU performance was made on the basis of a simulation model. Estimates of the processing time of one packet and the average throughput of the NPU model for each scenario are obtained.
ISSN:1818-1015
2313-5417