Architectural Advancement of Digital Low-Dropout Regulators
Digital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient fine-grained power delivery and management in system-on-chips (SoCs) due to their process scalability, ease of integration, and low-voltage operation. However, conventional DLDOs suffer gravely from the power-speed...
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doaj-aef5205a6fb449aba549d0b2b6ffe5532021-03-30T02:00:07ZengIEEEIEEE Access2169-35362020-01-01813783813785510.1109/ACCESS.2020.30124679151123Architectural Advancement of Digital Low-Dropout RegulatorsMuhammad Abrar Akram0https://orcid.org/0000-0001-7574-8695In-Chul Hwang1https://orcid.org/0000-0002-0045-9984Sohmyung Ha2https://orcid.org/0000-0003-3589-086XDivision of Engineering, New York University Abu Dhabi, Abu Dhabi, United Arab EmiratesDepartment of Electrical and Electronics Engineering, Kangwon National University, Chuncheon, South KoreaDivision of Engineering, New York University Abu Dhabi, Abu Dhabi, United Arab EmiratesDigital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient fine-grained power delivery and management in system-on-chips (SoCs) due to their process scalability, ease of integration, and low-voltage operation. However, conventional DLDOs suffer gravely from the power-speed tradeoff, which arises from the use of sampling clocks. To obtain reasonable performance in the undershoot and recovery during load transient states, a large output capacitor is inevitably required in these DLDOs. Moreover, they inherently involve large steady-state voltage ripples and poor power-supply rejection (PSR). These limitations of synchronous DLDOs and their counter measures are thoroughly discussed in this paper. Various design strategies of major building blocks, i.e. comparators and power transistor arrays, are explained in detail with examples. Architectural advances are also expounded including state-of-the-art DLDO architectures such as clock-boosted synchronous, analog-assisted synchronous, asynchornous, event-driven, and hybrid DLDOs. These state-of-the-art DLDOs do not only address the power-speed tradeoff and achieve fast load transient responses, but also can eliminate the use of an output capacitor in some cases. Moreover, some hybrid DLDOs successfully removed the steady state ripples and achieve high PSR. All of these DLDO are compared on basis of their performance metrics and figure-of-merits (FOMs).https://ieeexplore.ieee.org/document/9151123/Low-dropout regulatordigital LDOevent-driven LDOhybrid LDOasynchronous LDOoutput capacitor-less |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Muhammad Abrar Akram In-Chul Hwang Sohmyung Ha |
spellingShingle |
Muhammad Abrar Akram In-Chul Hwang Sohmyung Ha Architectural Advancement of Digital Low-Dropout Regulators IEEE Access Low-dropout regulator digital LDO event-driven LDO hybrid LDO asynchronous LDO output capacitor-less |
author_facet |
Muhammad Abrar Akram In-Chul Hwang Sohmyung Ha |
author_sort |
Muhammad Abrar Akram |
title |
Architectural Advancement of Digital Low-Dropout Regulators |
title_short |
Architectural Advancement of Digital Low-Dropout Regulators |
title_full |
Architectural Advancement of Digital Low-Dropout Regulators |
title_fullStr |
Architectural Advancement of Digital Low-Dropout Regulators |
title_full_unstemmed |
Architectural Advancement of Digital Low-Dropout Regulators |
title_sort |
architectural advancement of digital low-dropout regulators |
publisher |
IEEE |
series |
IEEE Access |
issn |
2169-3536 |
publishDate |
2020-01-01 |
description |
Digital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient fine-grained power delivery and management in system-on-chips (SoCs) due to their process scalability, ease of integration, and low-voltage operation. However, conventional DLDOs suffer gravely from the power-speed tradeoff, which arises from the use of sampling clocks. To obtain reasonable performance in the undershoot and recovery during load transient states, a large output capacitor is inevitably required in these DLDOs. Moreover, they inherently involve large steady-state voltage ripples and poor power-supply rejection (PSR). These limitations of synchronous DLDOs and their counter measures are thoroughly discussed in this paper. Various design strategies of major building blocks, i.e. comparators and power transistor arrays, are explained in detail with examples. Architectural advances are also expounded including state-of-the-art DLDO architectures such as clock-boosted synchronous, analog-assisted synchronous, asynchornous, event-driven, and hybrid DLDOs. These state-of-the-art DLDOs do not only address the power-speed tradeoff and achieve fast load transient responses, but also can eliminate the use of an output capacitor in some cases. Moreover, some hybrid DLDOs successfully removed the steady state ripples and achieve high PSR. All of these DLDO are compared on basis of their performance metrics and figure-of-merits (FOMs). |
topic |
Low-dropout regulator digital LDO event-driven LDO hybrid LDO asynchronous LDO output capacitor-less |
url |
https://ieeexplore.ieee.org/document/9151123/ |
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