A timing estimation algorithm for dPMR receiver based on FPGA and its implementation
The accuracy of symbol timing synchronization has a great impact on the demodulation performance of digital communication systems. The dPMR communication system requires the symbol synchronization of the receiver to have fast acquisition and good tracking performance. A timing estimation algorithm i...
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National Computer System Engineering Research Institute of China
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doaj-af8a09c4b4194bf4906fd4f3d73f2f0d2020-11-25T01:09:39ZzhoNational Computer System Engineering Research Institute of ChinaDianzi Jishu Yingyong0258-79982019-05-01455273010.16157/j.issn.0258-7998.1825903000101272A timing estimation algorithm for dPMR receiver based on FPGA and its implementationZhu Ziwen0Zhang Tao1Guan Hanxing2 Engineering Research Center of Metallurgical Automation and Measurement Technology, Wuhan University of Science and Technology,Wuhan 430081,China Engineering Research Center of Metallurgical Automation and Measurement Technology, Wuhan University of Science and Technology,Wuhan 430081,ChinaYangtze Optical Fibre and Cable Joint Stock Limited Company,Wuhan 430000,ChinaThe accuracy of symbol timing synchronization has a great impact on the demodulation performance of digital communication systems. The dPMR communication system requires the symbol synchronization of the receiver to have fast acquisition and good tracking performance. A timing estimation algorithm is proposed for this requirement. The algorithm combines the advantages of preamble timing algorithm and digital square filtering algorithm. Firstly, when the preamble of the burst information is captured, the preamble timing algorithm is used to implement high-precision fast timing estimation. Then, a digital square filtering algorithm is used to implement tracking correction for timing estimation at intervals of 384 symbols. At the same time, a simple FPGA implementation scheme is proposed. Compared with the classical matching filter timing algorithm based on synchronous waveform, it not only improves the demodulation performance of the receiver but also saves hardware resources.http://www.chinaaet.com/article/3000101272timing estimationfast acquisitiontiming trackingFPGA |
collection |
DOAJ |
language |
zho |
format |
Article |
sources |
DOAJ |
author |
Zhu Ziwen Zhang Tao Guan Hanxing |
spellingShingle |
Zhu Ziwen Zhang Tao Guan Hanxing A timing estimation algorithm for dPMR receiver based on FPGA and its implementation Dianzi Jishu Yingyong timing estimation fast acquisition timing tracking FPGA |
author_facet |
Zhu Ziwen Zhang Tao Guan Hanxing |
author_sort |
Zhu Ziwen |
title |
A timing estimation algorithm for dPMR receiver based on FPGA and its implementation |
title_short |
A timing estimation algorithm for dPMR receiver based on FPGA and its implementation |
title_full |
A timing estimation algorithm for dPMR receiver based on FPGA and its implementation |
title_fullStr |
A timing estimation algorithm for dPMR receiver based on FPGA and its implementation |
title_full_unstemmed |
A timing estimation algorithm for dPMR receiver based on FPGA and its implementation |
title_sort |
timing estimation algorithm for dpmr receiver based on fpga and its implementation |
publisher |
National Computer System Engineering Research Institute of China |
series |
Dianzi Jishu Yingyong |
issn |
0258-7998 |
publishDate |
2019-05-01 |
description |
The accuracy of symbol timing synchronization has a great impact on the demodulation performance of digital communication systems. The dPMR communication system requires the symbol synchronization of the receiver to have fast acquisition and good tracking performance. A timing estimation algorithm is proposed for this requirement. The algorithm combines the advantages of preamble timing algorithm and digital square filtering algorithm. Firstly, when the preamble of the burst information is captured, the preamble timing algorithm is used to implement high-precision fast timing estimation. Then, a digital square filtering algorithm is used to implement tracking correction for timing estimation at intervals of 384 symbols. At the same time, a simple FPGA implementation scheme is proposed. Compared with the classical matching filter timing algorithm based on synchronous waveform, it not only improves the demodulation performance of the receiver but also saves hardware resources. |
topic |
timing estimation fast acquisition timing tracking FPGA |
url |
http://www.chinaaet.com/article/3000101272 |
work_keys_str_mv |
AT zhuziwen atimingestimationalgorithmfordpmrreceiverbasedonfpgaanditsimplementation AT zhangtao atimingestimationalgorithmfordpmrreceiverbasedonfpgaanditsimplementation AT guanhanxing atimingestimationalgorithmfordpmrreceiverbasedonfpgaanditsimplementation AT zhuziwen timingestimationalgorithmfordpmrreceiverbasedonfpgaanditsimplementation AT zhangtao timingestimationalgorithmfordpmrreceiverbasedonfpgaanditsimplementation AT guanhanxing timingestimationalgorithmfordpmrreceiverbasedonfpgaanditsimplementation |
_version_ |
1725177494958505984 |