A Single Parameter Voltage Adjustable Immittance Topology for Integer- and Fractional-Order Design Using Modular Active CMOS Devices

A simple single parameter adjustable immittance concept designed with modular active devices, fabricated in I3T<inline-formula> <tex-math notation="LaTeX">$25~0.35~\mu \text{m}$ </tex-math></inline-formula> 3.3 V CMOS process of ON Semiconductor, is introduced. The...

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Main Authors: Roman Sotner, Jan Jerabek, Ladislav Polak, Roman Prokop, Winai Jaikla
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Access
Subjects:
Online Access:https://ieeexplore.ieee.org/document/9432958/
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spelling doaj-b6302541d267484296c31d734e5932b62021-06-02T23:18:33ZengIEEEIEEE Access2169-35362021-01-019737137372710.1109/ACCESS.2021.30811409432958A Single Parameter Voltage Adjustable Immittance Topology for Integer- and Fractional-Order Design Using Modular Active CMOS DevicesRoman Sotner0https://orcid.org/0000-0002-2430-1815Jan Jerabek1https://orcid.org/0000-0001-9487-5024Ladislav Polak2https://orcid.org/0000-0001-7084-6210Roman Prokop3https://orcid.org/0000-0002-5029-9878Winai Jaikla4https://orcid.org/0000-0003-1261-0917Department of Radio Electronics, FEEC, Brno University of Technology, Brno, Czech RepublicDepartment of Telecommunications, FEEC, Brno University of Technology, Brno, Czech RepublicDepartment of Radio Electronics, FEEC, Brno University of Technology, Brno, Czech RepublicDepartment of Microelectronics, FEEC, Brno University of Technology, Brno, Czech RepublicDepartment of Engineering Education, Faculty of Industrial Education and Technology, King Mongkut&#x2019;s Institute of Technology Ladkrabang, Bangkog, ThailandA simple single parameter adjustable immittance concept designed with modular active devices, fabricated in I3T<inline-formula> <tex-math notation="LaTeX">$25~0.35~\mu \text{m}$ </tex-math></inline-formula> 3.3 V CMOS process of ON Semiconductor, is introduced. The proposed devices employ an integer-order capacitor and specifically designed fractional-order capacitors (sometimes called constant phase elements). The proposed active topology consists of two simple active elements, namely a linearly voltage adjustable operational transconductance amplifier and a voltage differencing unity gain voltage follower/buffer, and only two passive elements, i.e. redundancy is minimized. The designed topology offers generation of an adjustable immittance having both the capacitive and inductive character. The importance of the order as well as the value of the pseudo-capacitance for design and analyzes are shown, including all important parasitic features for estimation of expected operational bandwidth which have to be considered in the design. The operational bandwidth is determined by high values of approximants of fractional-order capacities (225, 56 and <inline-formula> <tex-math notation="LaTeX">$8.8~\mu \text{F}$ </tex-math></inline-formula>/sec&#x005E;1-<inline-formula> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula>, where <inline-formula> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula> represents the order equal to 0.25, 0.5 and 0.75, respectively). These parameters result into ranges between tens of Hz and units-tens of kHz. The adjustability of the transconductance from 70 to <inline-formula> <tex-math notation="LaTeX">$700~\mu \text{S}$ </tex-math></inline-formula> by the driving voltage between 0.05 and 0.5 V offers approximately one decade change of equivalent capacitance and inductance. Laboratory-based experiments done with a fabricated prototype confirmed the theoretical presumptions.https://ieeexplore.ieee.org/document/9432958/Capacitance multiplierCMOSconstant phase elementfractional-orderimmittance generationlinear voltage adjustment
collection DOAJ
language English
format Article
sources DOAJ
author Roman Sotner
Jan Jerabek
Ladislav Polak
Roman Prokop
Winai Jaikla
spellingShingle Roman Sotner
Jan Jerabek
Ladislav Polak
Roman Prokop
Winai Jaikla
A Single Parameter Voltage Adjustable Immittance Topology for Integer- and Fractional-Order Design Using Modular Active CMOS Devices
IEEE Access
Capacitance multiplier
CMOS
constant phase element
fractional-order
immittance generation
linear voltage adjustment
author_facet Roman Sotner
Jan Jerabek
Ladislav Polak
Roman Prokop
Winai Jaikla
author_sort Roman Sotner
title A Single Parameter Voltage Adjustable Immittance Topology for Integer- and Fractional-Order Design Using Modular Active CMOS Devices
title_short A Single Parameter Voltage Adjustable Immittance Topology for Integer- and Fractional-Order Design Using Modular Active CMOS Devices
title_full A Single Parameter Voltage Adjustable Immittance Topology for Integer- and Fractional-Order Design Using Modular Active CMOS Devices
title_fullStr A Single Parameter Voltage Adjustable Immittance Topology for Integer- and Fractional-Order Design Using Modular Active CMOS Devices
title_full_unstemmed A Single Parameter Voltage Adjustable Immittance Topology for Integer- and Fractional-Order Design Using Modular Active CMOS Devices
title_sort single parameter voltage adjustable immittance topology for integer- and fractional-order design using modular active cmos devices
publisher IEEE
series IEEE Access
issn 2169-3536
publishDate 2021-01-01
description A simple single parameter adjustable immittance concept designed with modular active devices, fabricated in I3T<inline-formula> <tex-math notation="LaTeX">$25~0.35~\mu \text{m}$ </tex-math></inline-formula> 3.3 V CMOS process of ON Semiconductor, is introduced. The proposed devices employ an integer-order capacitor and specifically designed fractional-order capacitors (sometimes called constant phase elements). The proposed active topology consists of two simple active elements, namely a linearly voltage adjustable operational transconductance amplifier and a voltage differencing unity gain voltage follower/buffer, and only two passive elements, i.e. redundancy is minimized. The designed topology offers generation of an adjustable immittance having both the capacitive and inductive character. The importance of the order as well as the value of the pseudo-capacitance for design and analyzes are shown, including all important parasitic features for estimation of expected operational bandwidth which have to be considered in the design. The operational bandwidth is determined by high values of approximants of fractional-order capacities (225, 56 and <inline-formula> <tex-math notation="LaTeX">$8.8~\mu \text{F}$ </tex-math></inline-formula>/sec&#x005E;1-<inline-formula> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula>, where <inline-formula> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula> represents the order equal to 0.25, 0.5 and 0.75, respectively). These parameters result into ranges between tens of Hz and units-tens of kHz. The adjustability of the transconductance from 70 to <inline-formula> <tex-math notation="LaTeX">$700~\mu \text{S}$ </tex-math></inline-formula> by the driving voltage between 0.05 and 0.5 V offers approximately one decade change of equivalent capacitance and inductance. Laboratory-based experiments done with a fabricated prototype confirmed the theoretical presumptions.
topic Capacitance multiplier
CMOS
constant phase element
fractional-order
immittance generation
linear voltage adjustment
url https://ieeexplore.ieee.org/document/9432958/
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