A PARALLEL PIPELINED PACKET SWITCH ARCHITECTURE FOR MESH-CONNECTED MULTIPROCESSORS WITH INDEPENDENTLY ROUTED FLITS
In this paper, a packet switch architecture for mesh-connected multiprocessors based on the use of a set of in-put FIFO buffers and an output register matrix controlled by a novel distributed timing-based scheduling scheme is proposed. Simple static routing is assumed, with each packet split into a...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Scientific Research Support Fund of Jordan (SRSF) and Princess Sumaya University for Technology (PSUT)
2019-08-01
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| Series: | Jordanian Journal of Computers and Information Technology |
| Subjects: | |
| Online Access: | http://jjcit.org/Volume%2005,%20Number%2002/8-DOI%2010.5455-jjcit.71-1556375171.pdf |
| Summary: | In this paper, a packet switch architecture for mesh-connected multiprocessors based on the use of a set of in-put FIFO buffers and an output register matrix controlled by a novel distributed timing-based scheduling scheme is proposed. Simple static routing is assumed, with each packet split into a set of independently routed w-bit-wide flits. The device achieves at least 78% throughput for uniformly distributed traffic and an asymptot-ic higher bound of 100%. In contrast to the state-of-the-art VOQ-based switch architectures, the proposed switch is shown to reach its maximum throughput with no internal speedup required and has an order of mag-nitude lower hardware complexity. Compared to existing buffered crossbar non-VOQ switches with typical flit scheduling mechanisms, the proposed device demonstrates slightly higher throughput and substantially short-er delays in some practically important cases. |
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| ISSN: | 2413-9351 2415-1076 |