On Verification of PLC-Programs Written in the LD-Language

On Verification of PLC-Programs Written in the LD-Language

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We discuss some questions connected with the construction of a technology of analysing correctness of Programmable Logic Controller programs. We consider an example of modeling and automated verification of PLC-programs written in the Ladder Diagram language (including timed function blocks) of the...

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Bibliographic Details
Main Authors: E. V. Kuzmin, V. A. Sokolov
Format: Article
Language:English
Published: Yaroslavl State University 2015-02-01
Series:Modelirovanie i Analiz Informacionnyh Sistem
Subjects:
verification
model checking
plc-programs
ladder diagrams
Online Access:https://www.mais-journal.ru/jour/article/view/24

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