FPGA Implementation of Some Second Round NIST Lightweight Cryptography Candidates

• Main Authors: Brisbane Ovilla-Martínez, Cuauhtemoc Mancillas-López, Alberto F. Martínez-Herrera, José A. Bernal-Gutiérrez
• Format: Article
• Language: English
• Published: MDPI AG 2020-11-01
• Series: Electronics
• Subjects: NIST-lightweight cryptography; AEAD; FPGA
• Online Access: https://www.mdpi.com/2079-9292/9/11/1940

For almost one decade, the academic community has been working in the design and analysis of new lightweight primitives. This cryptography development aims to provide solutions tailored for resource-constrained devices. The U.S. National Institute of Standards and Technology (NIST) started an open process to create a Lightweight Cryptography Standardization portfolio. As a part of the process, the candidates must demonstrate their suitability for hardware implementation. Cost and performance are two of the criteria to be evaluated. In this work, we present the analysis of costs and performance in hardware implementations over five NIST LWC Round 2 candidates, COMET, ESTATE-AES/Gift, LOCUS, LOTUS, and Oribatida. Each candidate’s implementation was adapted to the Hardware API for Lightweight Cryptography for fair benchmarking of hardware cores. The results were generated for Xilinx Artix-7 xc7a12tcsg325-3. The results indicate that it is feasible to achieve the reduction of each solution below 2000 LUTs and 2000 slices where some of them (the variants of ESTATE-AES/Gift) are below 850 LUTs and 600 FF when they are included in the LWC CryptoCore.