Analysis of Memory System of Tiled Many-Core Processors
Tiled many-core processors are designed to integrate simple cores onto a single chip to take advantage of software-level parallelism, and these cores are interconnected via mesh-based networks to mitigate overheads such as limited throughput derived from traditional interconnects. As these processor...
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doaj-bf577c10517640b0b399ba3dcb95b6c52021-03-29T22:19:29ZengIEEEIEEE Access2169-35362019-01-017189641897710.1109/ACCESS.2019.28957018628953Analysis of Memory System of Tiled Many-Core ProcessorsYe Liu0https://orcid.org/0000-0003-0007-722XShinpei Kato1Masato Edahiro2Graduate School of Information Science, Nagoya University, Nagoya, JapanGraduate School of Information Science and Technology, The University of Tokyo, Tokyo, JapanGraduate School of Information Science, Nagoya University, Nagoya, JapanTiled many-core processors are designed to integrate simple cores onto a single chip to take advantage of software-level parallelism, and these cores are interconnected via mesh-based networks to mitigate overheads such as limited throughput derived from traditional interconnects. As these processors become more prevalent, one unnoticed problem is that it is more likely for operating system (OS) designers to believe that these processors, which have multiple on-chip memory controllers, belong to the non-uniform memory access (NUMA) system. In this paper, we define novel models regarding the differentiation between uniform memory access and NUMA on tiled many-core processors from the perspective of the cache system to facilitate OS designers and application programmers in fully understanding the underlying hardware. Whether or not a tiled many-core processor belongs to the NUMA system, is determined by the cache system rather than how many memory controllers it has. The experimental results together with the novel models are able to explain why the (non-)significant performance difference can be observed on KNL and TILE-Gx72.https://ieeexplore.ieee.org/document/8628953/NUMAUMAmemory systemtiled many-core processorss |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Ye Liu Shinpei Kato Masato Edahiro |
spellingShingle |
Ye Liu Shinpei Kato Masato Edahiro Analysis of Memory System of Tiled Many-Core Processors IEEE Access NUMA UMA memory system tiled many-core processorss |
author_facet |
Ye Liu Shinpei Kato Masato Edahiro |
author_sort |
Ye Liu |
title |
Analysis of Memory System of Tiled Many-Core Processors |
title_short |
Analysis of Memory System of Tiled Many-Core Processors |
title_full |
Analysis of Memory System of Tiled Many-Core Processors |
title_fullStr |
Analysis of Memory System of Tiled Many-Core Processors |
title_full_unstemmed |
Analysis of Memory System of Tiled Many-Core Processors |
title_sort |
analysis of memory system of tiled many-core processors |
publisher |
IEEE |
series |
IEEE Access |
issn |
2169-3536 |
publishDate |
2019-01-01 |
description |
Tiled many-core processors are designed to integrate simple cores onto a single chip to take advantage of software-level parallelism, and these cores are interconnected via mesh-based networks to mitigate overheads such as limited throughput derived from traditional interconnects. As these processors become more prevalent, one unnoticed problem is that it is more likely for operating system (OS) designers to believe that these processors, which have multiple on-chip memory controllers, belong to the non-uniform memory access (NUMA) system. In this paper, we define novel models regarding the differentiation between uniform memory access and NUMA on tiled many-core processors from the perspective of the cache system to facilitate OS designers and application programmers in fully understanding the underlying hardware. Whether or not a tiled many-core processor belongs to the NUMA system, is determined by the cache system rather than how many memory controllers it has. The experimental results together with the novel models are able to explain why the (non-)significant performance difference can be observed on KNL and TILE-Gx72. |
topic |
NUMA UMA memory system tiled many-core processorss |
url |
https://ieeexplore.ieee.org/document/8628953/ |
work_keys_str_mv |
AT yeliu analysisofmemorysystemoftiledmanycoreprocessors AT shinpeikato analysisofmemorysystemoftiledmanycoreprocessors AT masatoedahiro analysisofmemorysystemoftiledmanycoreprocessors |
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1724191893910192128 |