In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache manageme...
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doaj-c2e5e4cc4fc740f7850d3acf2d0565fd2020-11-25T02:00:08ZengMDPI AGMicromachines2072-666X2019-02-0110212410.3390/mi10020124mi10020124In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMsHo Hyun Shin0Eui-Young Chung1Samsung Electronics Company, Ltd., Hwasung 18448, KoreaSchool of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, KoreaRecently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache management techniques and latency hiding schemes to reduce DRAM access time, in a high-performance system using high-capacity 3D-stacked DRAM, it is ultimately essential to reduce the latency of the DRAM itself. To solve this problem, various asymmetric in-DRAM cache structures have recently been proposed, which are more attractive for high-capacity DRAMs because they can be implemented at a lower cost in 3D-stacked DRAMs. However, most research mainly focuses on the architecture of the in-DRAM cache itself and does not pay much attention to proper management methods. In this paper, we propose two new management algorithms for the in-DRAM caches to achieve a low-latency and low-power 3D-stacked DRAM device. Through the computing system simulation, we demonstrate the improvement of energy delay product up to 67%.https://www.mdpi.com/2072-666X/10/2/1243D-stackedDRAMin-DRAM cachelow-latencylow-power |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Ho Hyun Shin Eui-Young Chung |
spellingShingle |
Ho Hyun Shin Eui-Young Chung In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs Micromachines 3D-stacked DRAM in-DRAM cache low-latency low-power |
author_facet |
Ho Hyun Shin Eui-Young Chung |
author_sort |
Ho Hyun Shin |
title |
In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs |
title_short |
In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs |
title_full |
In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs |
title_fullStr |
In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs |
title_full_unstemmed |
In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs |
title_sort |
in-dram cache management for low latency and low power 3d-stacked drams |
publisher |
MDPI AG |
series |
Micromachines |
issn |
2072-666X |
publishDate |
2019-02-01 |
description |
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache management techniques and latency hiding schemes to reduce DRAM access time, in a high-performance system using high-capacity 3D-stacked DRAM, it is ultimately essential to reduce the latency of the DRAM itself. To solve this problem, various asymmetric in-DRAM cache structures have recently been proposed, which are more attractive for high-capacity DRAMs because they can be implemented at a lower cost in 3D-stacked DRAMs. However, most research mainly focuses on the architecture of the in-DRAM cache itself and does not pay much attention to proper management methods. In this paper, we propose two new management algorithms for the in-DRAM caches to achieve a low-latency and low-power 3D-stacked DRAM device. Through the computing system simulation, we demonstrate the improvement of energy delay product up to 67%. |
topic |
3D-stacked DRAM in-DRAM cache low-latency low-power |
url |
https://www.mdpi.com/2072-666X/10/2/124 |
work_keys_str_mv |
AT hohyunshin indramcachemanagementforlowlatencyandlowpower3dstackeddrams AT euiyoungchung indramcachemanagementforlowlatencyandlowpower3dstackeddrams |
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