Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators

Abstract New theoretical lower bounds for the number of operators needed in fixed-point constant multiplication blocks are presented. The multipliers are constructed with the shift-and-add approach, where every arithmetic operation is pipelined, and with the generalization that n-input pipelined add...

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Main Authors:	Miriam Guadalupe Cruz Jiménez, Uwe Meyer Baese, Gordana Jovanovic Dolecek
Format:	Article
Language:	English
Published:	SpringerOpen 2017-05-01
Series:	EURASIP Journal on Advances in Signal Processing
Subjects:	SCM MCM FPGA Multiplication Lower bound
Online Access:	http://link.springer.com/article/10.1186/s13634-017-0466-z

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spelling	doaj-cac28dd71a81476cbdee68aac4324b092020-11-24T22:01:11ZengSpringerOpenEURASIP Journal on Advances in Signal Processing1687-61802017-05-012017111310.1186/s13634-017-0466-zTheoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operatorsMiriam Guadalupe Cruz Jiménez0Uwe Meyer Baese1Gordana Jovanovic Dolecek2Department of Electronics, Institute INAOEElectrical and Computer Engineering Department, Florida State UniversityDepartment of Electronics, Institute INAOEAbstract New theoretical lower bounds for the number of operators needed in fixed-point constant multiplication blocks are presented. The multipliers are constructed with the shift-and-add approach, where every arithmetic operation is pipelined, and with the generalization that n-input pipelined additions/subtractions are allowed, along with pure pipelining registers. These lower bounds, tighter than the state-of-the-art theoretical limits, are particularly useful in early design stages for a quick assessment in the hardware utilization of low-cost constant multiplication blocks implemented in the newest families of field programmable gate array (FPGA) integrated circuits.http://link.springer.com/article/10.1186/s13634-017-0466-zSCMMCMFPGAMultiplicationLower bound
collection	DOAJ
language	English
format	Article
sources	DOAJ
author	Miriam Guadalupe Cruz Jiménez Uwe Meyer Baese Gordana Jovanovic Dolecek
spellingShingle	Miriam Guadalupe Cruz Jiménez Uwe Meyer Baese Gordana Jovanovic Dolecek Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators EURASIP Journal on Advances in Signal Processing SCM MCM FPGA Multiplication Lower bound
author_facet	Miriam Guadalupe Cruz Jiménez Uwe Meyer Baese Gordana Jovanovic Dolecek
author_sort	Miriam Guadalupe Cruz Jiménez
title	Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators
title_short	Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators
title_full	Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators
title_fullStr	Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators
title_full_unstemmed	Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators
title_sort	theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators
publisher	SpringerOpen
series	EURASIP Journal on Advances in Signal Processing
issn	1687-6180
publishDate	2017-05-01
description	Abstract New theoretical lower bounds for the number of operators needed in fixed-point constant multiplication blocks are presented. The multipliers are constructed with the shift-and-add approach, where every arithmetic operation is pipelined, and with the generalization that n-input pipelined additions/subtractions are allowed, along with pure pipelining registers. These lower bounds, tighter than the state-of-the-art theoretical limits, are particularly useful in early design stages for a quick assessment in the hardware utilization of low-cost constant multiplication blocks implemented in the newest families of field programmable gate array (FPGA) integrated circuits.
topic	SCM MCM FPGA Multiplication Lower bound
url	http://link.springer.com/article/10.1186/s13634-017-0466-z
work_keys_str_mv	AT miriamguadalupecruzjimenez theoreticallowerboundsforparallelpipelinedshiftandaddconstantmultiplicationswithninputarithmeticoperators AT uwemeyerbaese theoreticallowerboundsforparallelpipelinedshiftandaddconstantmultiplicationswithninputarithmeticoperators AT gordanajovanovicdolecek theoreticallowerboundsforparallelpipelinedshiftandaddconstantmultiplicationswithninputarithmeticoperators
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Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators

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