Sparse Cholesky Factorization on FPGA Using Parameterized Model

• Main Authors: Yichun Sun, Hengzhu Liu, Tong Zhou
• Format: Article
• Language: English
• Published: Hindawi Limited 2017-01-01
• Series: Mathematical Problems in Engineering
• Online Access: http://dx.doi.org/10.1155/2017/3021591
• ISSN: 1024-123X; 1563-5147

Cholesky factorization is a fundamental problem in most engineering and science computation applications. When dealing with a large sparse matrix, numerical decomposition consumes the most time. We present a vector architecture to parallelize numerical decomposition of Cholesky factorization. We construct an integrated analytical parameterized performance model to accurately predict the execution times of typical matrices under varying parameters. Our proposed approach is general for accelerator and limited by neither field-programmable gate arrays (FPGAs) nor application-specific integrated circuit. We implement a simplified module in FPGAs to prove the accuracy of the model. The experiments show that, for most cases, the performance differences between the predicted and measured execution are less than 10%. Based on the performance model, we optimize parameters and obtain a balance of resources and performance after analyzing the performance of varied parameter settings. Comparing with the state-of-the-art implementation in CPU and GPU, we find that the performance of the optimal parameters is 2x that of CPU. Our model offers several advantages, particularly in power consumption. It provides guidance for the design of future acceleration components.