Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

This article presents a method for analyzing the parasitic effects of interconnects on the performance of the STT-MTJ-based computational random access memory (CRAM) in-memory computation platform. The CRAM is a platform that makes a small reconfiguration to a standard spintronics-based memory array...

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Main Authors:	Masoud Zabihi, Arvind K. Sharma, Meghna G. Mankalale, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Salonik Resch, Ulya R. Karpuzcu, Jian-Ping Wang, Sachin S. Sapatnekar
Format:	Article
Language:	English
Published:	IEEE 2020-01-01
Series:	IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Subjects:	In-memory computing spin-transfer torque computational random access memory (STT-CRAM) spintronics
Online Access:	https://ieeexplore.ieee.org/document/9056847/

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spelling	doaj-e2947372c0da43b6b30bc48893c20bb72021-03-29T18:54:18ZengIEEEIEEE Journal on Exploratory Solid-State Computational Devices and Circuits2329-92312020-01-0161717910.1109/JXCDC.2020.29853149056847Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational PlatformMasoud Zabihi0https://orcid.org/0000-0003-1916-901XArvind K. Sharma1Meghna G. Mankalale2https://orcid.org/0000-0002-6757-9649Zamshed Iqbal Chowdhury3https://orcid.org/0000-0002-4096-7000Zhengyang Zhao4https://orcid.org/0000-0002-8017-3635Salonik Resch5Ulya R. Karpuzcu6Jian-Ping Wang7https://orcid.org/0000-0003-2815-6624Sachin S. Sapatnekar8https://orcid.org/0000-0002-5353-2364Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USADepartment of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USADepartment of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USADepartment of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USADepartment of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USADepartment of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USADepartment of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USADepartment of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USADepartment of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USAThis article presents a method for analyzing the parasitic effects of interconnects on the performance of the STT-MTJ-based computational random access memory (CRAM) in-memory computation platform. The CRAM is a platform that makes a small reconfiguration to a standard spintronics-based memory array to enable logic operations within the array. The analytical method in this article develops a methodology that quantifies the way in which wire parasitics limit the size and configuration of a CRAM array and studies the impact of cell- and array-level design choices on the CRAM noise margin. Finally, the method determines the maximum allowable CRAM array size under various technology considerations.https://ieeexplore.ieee.org/document/9056847/In-memory computingspin-transfer torque computational random access memory (STT-CRAM)spintronics
collection	DOAJ
language	English
format	Article
sources	DOAJ
author	Masoud Zabihi Arvind K. Sharma Meghna G. Mankalale Zamshed Iqbal Chowdhury Zhengyang Zhao Salonik Resch Ulya R. Karpuzcu Jian-Ping Wang Sachin S. Sapatnekar
spellingShingle	Masoud Zabihi Arvind K. Sharma Meghna G. Mankalale Zamshed Iqbal Chowdhury Zhengyang Zhao Salonik Resch Ulya R. Karpuzcu Jian-Ping Wang Sachin S. Sapatnekar Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform IEEE Journal on Exploratory Solid-State Computational Devices and Circuits In-memory computing spin-transfer torque computational random access memory (STT-CRAM) spintronics
author_facet	Masoud Zabihi Arvind K. Sharma Meghna G. Mankalale Zamshed Iqbal Chowdhury Zhengyang Zhao Salonik Resch Ulya R. Karpuzcu Jian-Ping Wang Sachin S. Sapatnekar
author_sort	Masoud Zabihi
title	Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform
title_short	Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform
title_full	Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform
title_fullStr	Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform
title_full_unstemmed	Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform
title_sort	analyzing the effects of interconnect parasitics in the stt cram in-memory computational platform
publisher	IEEE
series	IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
issn	2329-9231
publishDate	2020-01-01
description	This article presents a method for analyzing the parasitic effects of interconnects on the performance of the STT-MTJ-based computational random access memory (CRAM) in-memory computation platform. The CRAM is a platform that makes a small reconfiguration to a standard spintronics-based memory array to enable logic operations within the array. The analytical method in this article develops a methodology that quantifies the way in which wire parasitics limit the size and configuration of a CRAM array and studies the impact of cell- and array-level design choices on the CRAM noise margin. Finally, the method determines the maximum allowable CRAM array size under various technology considerations.
topic	In-memory computing spin-transfer torque computational random access memory (STT-CRAM) spintronics
url	https://ieeexplore.ieee.org/document/9056847/
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Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

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