An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology
This study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-t...
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MDPI AG
2021-07-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/10/14/1686 |
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doaj-e4009ec1097040cf8e90a3fc050d36d92021-07-23T13:38:12ZengMDPI AGElectronics2079-92922021-07-01101686168610.3390/electronics10141686An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS TechnologyJian Chen0Wei Zhang1Qingqing Sun2Lizheng Liu3State Key Laboratory of ASIC (Application-Specific Integrated Circuit) System, School of Microelectronics, Fudan University, Shanghai 200433, ChinaState Key Laboratory of ASIC (Application-Specific Integrated Circuit) System, School of Microelectronics, Fudan University, Shanghai 200433, ChinaState Key Laboratory of ASIC (Application-Specific Integrated Circuit) System, School of Microelectronics, Fudan University, Shanghai 200433, ChinaSchool of Information Science and Technology, Fudan University, Shanghai 200433, ChinaThis study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-tuning range to ensure that the LC PLL achieves multiprotocol serial link coverage from 8 to 12.5 Gbps. Two switch capacitor array-based LC VCOs have a large frequency-tuning range and small VCO gain. The noise-reduced LDO regulator provides a very low-noise power supply to the VCO. The active area occupied by the proposed LC PLL in UMC 28-nm 1P10M complementary metal–oxide–semiconductor (CMOS) technology is 0.25 mm<sup>2</sup>. The phase noise of the VCO at 1 MHz is −108.1 dBc/Hz. The power consumption of the LC PLL with a 1.8-V supply is 16.5 mW.https://www.mdpi.com/2079-9292/10/14/1686Multiprotocol SERDESLC PLLnoise-reduced LDO regulatordual VCO |
| collection |
DOAJ |
| language |
English |
| format |
Article |
| sources |
DOAJ |
| author |
Jian Chen Wei Zhang Qingqing Sun Lizheng Liu |
| spellingShingle |
Jian Chen Wei Zhang Qingqing Sun Lizheng Liu An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology Electronics Multiprotocol SERDES LC PLL noise-reduced LDO regulator dual VCO |
| author_facet |
Jian Chen Wei Zhang Qingqing Sun Lizheng Liu |
| author_sort |
Jian Chen |
| title |
An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology |
| title_short |
An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology |
| title_full |
An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology |
| title_fullStr |
An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology |
| title_full_unstemmed |
An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology |
| title_sort |
8–12.5-ghz lc pll with dual vco and noise-reduced ldo regulator for multilane multiprotocol serdes in 28-nm cmos technology |
| publisher |
MDPI AG |
| series |
Electronics |
| issn |
2079-9292 |
| publishDate |
2021-07-01 |
| description |
This study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-tuning range to ensure that the LC PLL achieves multiprotocol serial link coverage from 8 to 12.5 Gbps. Two switch capacitor array-based LC VCOs have a large frequency-tuning range and small VCO gain. The noise-reduced LDO regulator provides a very low-noise power supply to the VCO. The active area occupied by the proposed LC PLL in UMC 28-nm 1P10M complementary metal–oxide–semiconductor (CMOS) technology is 0.25 mm<sup>2</sup>. The phase noise of the VCO at 1 MHz is −108.1 dBc/Hz. The power consumption of the LC PLL with a 1.8-V supply is 16.5 mW. |
| topic |
Multiprotocol SERDES LC PLL noise-reduced LDO regulator dual VCO |
| url |
https://www.mdpi.com/2079-9292/10/14/1686 |
| work_keys_str_mv |
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