An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology

An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology

This study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-t...

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Bibliographic Details
Main Authors: Jian Chen, Wei Zhang, Qingqing Sun, Lizheng Liu
Format: Article
Language:English
Published: MDPI AG 2021-07-01
Series:Electronics
Subjects:
Multiprotocol SERDES
LC PLL
noise-reduced LDO regulator
dual VCO
Online Access:https://www.mdpi.com/2079-9292/10/14/1686

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