Red de Procesadores Evolutivos para solucionar el Problema de los Tres Colores. Implementación en Hardware.
In this paper, a Network of Evolutionary Processors (NEP) is implemented, to solve the problem of the three colors. To achieve implementation, it was used as an FPGA hardware resource. The main objective of this work is to demonstrate the feasibility of the physical implement...
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doaj-ea05f145d40646a9a3c60c99ad0843672020-11-25T02:18:57ZspaUniversidad de Ciencias InformáticasRevista Cubana de Ciencias Informáticas1994-15362227-18992015-10-0194155170Red de Procesadores Evolutivos para solucionar el Problema de los Tres Colores. Implementación en Hardware.José Antonio Castaño Guevara0Valery Moreno1Alejandro Cabrera2Abraham Gutiérrez3Víctor Martínez4Universidad de las Ciencias Informáticas. Carretera a San Antonio de los Baños, km 2 ½, Torrens, Boyeros, La Habana, Cuba. CP.: 19370.Instituto Superior Politécnico José Antonio Echeverría . Cuba. Instituto Superior Politécnico José Antonio Echeverría . Cuba. Universidad Politécnica de Madrid, España . Universidad Politécnica de Madrid, España . In this paper, a Network of Evolutionary Processors (NEP) is implemented, to solve the problem of the three colors. To achieve implementation, it was used as an FPGA hardware resource. The main objective of this work is to demonstrate the feasibility of the physical implementation of parallel algorithms to solve problems NP -complete. With this implementation is achieved that the implementation of the solution to be made reliably, quickly and efficiently. The project was developed using the Xilinx ISE 12.1 tool, using hardware description language to VHDL. For the simulation tool was used ISim 12.1, also from Xilinx. The results were tested using the platform Atlys Board Company which contains a Digilent Spartan-6 LX45 FPGA, Xilinx also. Images of the tool used, the Test Kit and simulation perf ormed and a table of data showing that the implementation of this complex algorithm used very few FPGA resources used are shown.http://rcci.uci.cu/index.php?journal=rcci&page=article&op=view&path[]=1193&path[]=388NEPFPGAVHDLComplex ProblemParallel Procesing |
collection |
DOAJ |
language |
Spanish |
format |
Article |
sources |
DOAJ |
author |
José Antonio Castaño Guevara Valery Moreno Alejandro Cabrera Abraham Gutiérrez Víctor Martínez |
spellingShingle |
José Antonio Castaño Guevara Valery Moreno Alejandro Cabrera Abraham Gutiérrez Víctor Martínez Red de Procesadores Evolutivos para solucionar el Problema de los Tres Colores. Implementación en Hardware. Revista Cubana de Ciencias Informáticas NEP FPGA VHDL Complex Problem Parallel Procesing |
author_facet |
José Antonio Castaño Guevara Valery Moreno Alejandro Cabrera Abraham Gutiérrez Víctor Martínez |
author_sort |
José Antonio Castaño Guevara |
title |
Red de Procesadores Evolutivos para solucionar el Problema de los Tres Colores. Implementación en Hardware. |
title_short |
Red de Procesadores Evolutivos para solucionar el Problema de los Tres Colores. Implementación en Hardware. |
title_full |
Red de Procesadores Evolutivos para solucionar el Problema de los Tres Colores. Implementación en Hardware. |
title_fullStr |
Red de Procesadores Evolutivos para solucionar el Problema de los Tres Colores. Implementación en Hardware. |
title_full_unstemmed |
Red de Procesadores Evolutivos para solucionar el Problema de los Tres Colores. Implementación en Hardware. |
title_sort |
red de procesadores evolutivos para solucionar el problema de los tres colores. implementación en hardware. |
publisher |
Universidad de Ciencias Informáticas |
series |
Revista Cubana de Ciencias Informáticas |
issn |
1994-1536 2227-1899 |
publishDate |
2015-10-01 |
description |
In this paper, a Network of Evolutionary Processors (NEP) is implemented, to solve the problem of the three colors. To achieve implementation, it was used as an FPGA hardware resource. The main objective of this work is to demonstrate the feasibility of the physical implementation of parallel algorithms to solve problems NP -complete. With this implementation is achieved that the implementation of the solution to be made reliably, quickly and efficiently. The project was developed using the Xilinx ISE 12.1 tool, using hardware description language to VHDL.
For the simulation tool was used ISim 12.1, also from Xilinx. The results were tested using the platform Atlys Board Company which contains a Digilent Spartan-6 LX45 FPGA, Xilinx also. Images of the tool used, the Test Kit and
simulation perf ormed and a table of data showing that the implementation of this complex algorithm used very few
FPGA resources used are shown. |
topic |
NEP FPGA VHDL Complex Problem Parallel Procesing |
url |
http://rcci.uci.cu/index.php?journal=rcci&page=article&op=view&path[]=1193&path[]=388 |
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