A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study
Integrated circuits may be vulnerable to hardware Trojan attacks during its design or fabrication phases. This article is a case study of the design of a Viterbi decoder and the effect of hardware Trojans on a coded communication system employing the Viterbi decoder. Design of a Viterbi decoder and...
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doaj-edd394f384d341fc9948ee361fcd6b702020-11-25T00:18:42ZengPeerJ Inc.PeerJ Computer Science2376-59922020-03-016e25010.7717/peerj-cs.250A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation studyVarsha Kakkara0Karthi Balasubramanian1B. Yamuna2Deepak Mishra3Karthikeyan Lingasubramanian4Senthil Murugan5Department of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, Tamil Nadu, IndiaDepartment of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, Tamil Nadu, IndiaDepartment of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, Tamil Nadu, IndiaDigital Communication Division (DCD), Optical and Digital Communication Group (ODCG), Satcom Navigation Payload Area (SNPA), Space Application Center (SAC), ISRO, Ahmedabad, Gujarat, IndiaElectrical and Computer Engineering, University of Alabama, Birmingham, AL, USADepartment of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Amritapuri, Kerala, IndiaIntegrated circuits may be vulnerable to hardware Trojan attacks during its design or fabrication phases. This article is a case study of the design of a Viterbi decoder and the effect of hardware Trojans on a coded communication system employing the Viterbi decoder. Design of a Viterbi decoder and possible hardware Trojan models for the same are proposed. An FPGA-based implementation of the decoder and the associated Trojan circuits have been discussed. The noise-added encoded input data stream is stored in the block RAM of the FPGA and the decoded data stream is monitored on the PC through an universal asynchronous receiver transmitter interface. The implementation results show that there is barely any change in the LUTs used (0.5%) and power dissipation (3%) due to the insertion of the proposed Trojan circuits, thus establishing the surreptitious nature of the Trojan. In spite of the fact that the Trojans cause negligible changes in the circuit parameters, there are significant changes in the bit error rate (BER) due to the presence of Trojans. In the absence of Trojans, BER drops down to zero for signal to noise rations (SNRs) higher than 6 dB, but with the presence of Trojans, BER doesn’t reduce to zero even at a very high SNRs. This is true even with the Trojan being activated only once during the entire duration of the transmission.https://peerj.com/articles/cs-250.pdfCoded communication systemHardware TrojanViterbi decoderBit error rate |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Varsha Kakkara Karthi Balasubramanian B. Yamuna Deepak Mishra Karthikeyan Lingasubramanian Senthil Murugan |
spellingShingle |
Varsha Kakkara Karthi Balasubramanian B. Yamuna Deepak Mishra Karthikeyan Lingasubramanian Senthil Murugan A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study PeerJ Computer Science Coded communication system Hardware Trojan Viterbi decoder Bit error rate |
author_facet |
Varsha Kakkara Karthi Balasubramanian B. Yamuna Deepak Mishra Karthikeyan Lingasubramanian Senthil Murugan |
author_sort |
Varsha Kakkara |
title |
A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study |
title_short |
A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study |
title_full |
A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study |
title_fullStr |
A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study |
title_full_unstemmed |
A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study |
title_sort |
viterbi decoder and its hardware trojan models: an fpga-based implementation study |
publisher |
PeerJ Inc. |
series |
PeerJ Computer Science |
issn |
2376-5992 |
publishDate |
2020-03-01 |
description |
Integrated circuits may be vulnerable to hardware Trojan attacks during its design or fabrication phases. This article is a case study of the design of a Viterbi decoder and the effect of hardware Trojans on a coded communication system employing the Viterbi decoder. Design of a Viterbi decoder and possible hardware Trojan models for the same are proposed. An FPGA-based implementation of the decoder and the associated Trojan circuits have been discussed. The noise-added encoded input data stream is stored in the block RAM of the FPGA and the decoded data stream is monitored on the PC through an universal asynchronous receiver transmitter interface. The implementation results show that there is barely any change in the LUTs used (0.5%) and power dissipation (3%) due to the insertion of the proposed Trojan circuits, thus establishing the surreptitious nature of the Trojan. In spite of the fact that the Trojans cause negligible changes in the circuit parameters, there are significant changes in the bit error rate (BER) due to the presence of Trojans. In the absence of Trojans, BER drops down to zero for signal to noise rations (SNRs) higher than 6 dB, but with the presence of Trojans, BER doesn’t reduce to zero even at a very high SNRs. This is true even with the Trojan being activated only once during the entire duration of the transmission. |
topic |
Coded communication system Hardware Trojan Viterbi decoder Bit error rate |
url |
https://peerj.com/articles/cs-250.pdf |
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