A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study

A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study

Integrated circuits may be vulnerable to hardware Trojan attacks during its design or fabrication phases. This article is a case study of the design of a Viterbi decoder and the effect of hardware Trojans on a coded communication system employing the Viterbi decoder. Design of a Viterbi decoder and...

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Bibliographic Details
Main Authors: Varsha Kakkara, Karthi Balasubramanian, B. Yamuna, Deepak Mishra, Karthikeyan Lingasubramanian, Senthil Murugan
Format: Article
Language:English
Published: PeerJ Inc. 2020-03-01
Series:PeerJ Computer Science
Subjects:
Coded communication system
Hardware Trojan
Viterbi decoder
Bit error rate
Online Access:https://peerj.com/articles/cs-250.pdf

Internet

https://peerj.com/articles/cs-250.pdf

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