Modeling and Implementation of a Power Estimation Methodology for SystemC
This work describes a methodology to model power consumption of logic modules. A detailed mathematical model is presented and incorporated in a tool for translation of models written in VHDL to SystemC. The functionality for implicit power monitoring and estimation is inserted at module translation....
Main Authors: | , , , |
---|---|
Format: | Article |
Language: | English |
Published: |
Hindawi Limited
2012-01-01
|
Series: | International Journal of Reconfigurable Computing |
Online Access: | http://dx.doi.org/10.1155/2012/439727 |
Summary: | This work describes a methodology to model power
consumption of logic modules. A detailed mathematical model
is presented and incorporated in a tool for translation of
models written in VHDL to SystemC. The functionality for
implicit power monitoring and estimation is inserted at module
translation. The translation further implements an approach to
wrap RTL to TLM interfaces so that the translated module can
be connected to a system-level simulator. The power analysis is
based on a statistical model of the underlying HW structure
and an analysis of input data. The flexibility of the C++
syntax is exploited, to integrate the power evaluation technique.
The accuracy and speed-up of the approach are illustrated and
compared to a conventional power analysis flow using PPR
simulation, based on Xilinx technology. |
---|---|
ISSN: | 1687-7195 1687-7209 |