Modeling and Implementation of a Power Estimation Methodology for SystemC
This work describes a methodology to model power consumption of logic modules. A detailed mathematical model is presented and incorporated in a tool for translation of models written in VHDL to SystemC. The functionality for implicit power monitoring and estimation is inserted at module translation....
Main Authors: | , , , |
---|---|
Format: | Article |
Language: | English |
Published: |
Hindawi Limited
2012-01-01
|
Series: | International Journal of Reconfigurable Computing |
Online Access: | http://dx.doi.org/10.1155/2012/439727 |
id |
doaj-ee88775d176c48dea644671340a6a5e1 |
---|---|
record_format |
Article |
spelling |
doaj-ee88775d176c48dea644671340a6a5e12020-11-24T23:04:30ZengHindawi LimitedInternational Journal of Reconfigurable Computing1687-71951687-72092012-01-01201210.1155/2012/439727439727Modeling and Implementation of a Power Estimation Methodology for SystemCMatthias Kuehnle0Andre Wagner1Alisson V. Brito2Juergen Becker3Institute for Information Processing Technology, KIT, 7602 Karlsruhe, GermanyInstitute for Information Processing Technology, KIT, 7602 Karlsruhe, GermanyDepartment of Informatics, Federal University of Paraiba (UFPB), 58051-900 João Pessoa, PB, BrazilInstitute for Information Processing Technology, KIT, 7602 Karlsruhe, GermanyThis work describes a methodology to model power consumption of logic modules. A detailed mathematical model is presented and incorporated in a tool for translation of models written in VHDL to SystemC. The functionality for implicit power monitoring and estimation is inserted at module translation. The translation further implements an approach to wrap RTL to TLM interfaces so that the translated module can be connected to a system-level simulator. The power analysis is based on a statistical model of the underlying HW structure and an analysis of input data. The flexibility of the C++ syntax is exploited, to integrate the power evaluation technique. The accuracy and speed-up of the approach are illustrated and compared to a conventional power analysis flow using PPR simulation, based on Xilinx technology.http://dx.doi.org/10.1155/2012/439727 |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Matthias Kuehnle Andre Wagner Alisson V. Brito Juergen Becker |
spellingShingle |
Matthias Kuehnle Andre Wagner Alisson V. Brito Juergen Becker Modeling and Implementation of a Power Estimation Methodology for SystemC International Journal of Reconfigurable Computing |
author_facet |
Matthias Kuehnle Andre Wagner Alisson V. Brito Juergen Becker |
author_sort |
Matthias Kuehnle |
title |
Modeling and Implementation of a Power Estimation Methodology for SystemC |
title_short |
Modeling and Implementation of a Power Estimation Methodology for SystemC |
title_full |
Modeling and Implementation of a Power Estimation Methodology for SystemC |
title_fullStr |
Modeling and Implementation of a Power Estimation Methodology for SystemC |
title_full_unstemmed |
Modeling and Implementation of a Power Estimation Methodology for SystemC |
title_sort |
modeling and implementation of a power estimation methodology for systemc |
publisher |
Hindawi Limited |
series |
International Journal of Reconfigurable Computing |
issn |
1687-7195 1687-7209 |
publishDate |
2012-01-01 |
description |
This work describes a methodology to model power
consumption of logic modules. A detailed mathematical model
is presented and incorporated in a tool for translation of
models written in VHDL to SystemC. The functionality for
implicit power monitoring and estimation is inserted at module
translation. The translation further implements an approach to
wrap RTL to TLM interfaces so that the translated module can
be connected to a system-level simulator. The power analysis is
based on a statistical model of the underlying HW structure
and an analysis of input data. The flexibility of the C++
syntax is exploited, to integrate the power evaluation technique.
The accuracy and speed-up of the approach are illustrated and
compared to a conventional power analysis flow using PPR
simulation, based on Xilinx technology. |
url |
http://dx.doi.org/10.1155/2012/439727 |
work_keys_str_mv |
AT matthiaskuehnle modelingandimplementationofapowerestimationmethodologyforsystemc AT andrewagner modelingandimplementationofapowerestimationmethodologyforsystemc AT alissonvbrito modelingandimplementationofapowerestimationmethodologyforsystemc AT juergenbecker modelingandimplementationofapowerestimationmethodologyforsystemc |
_version_ |
1725629937455464448 |