A CRC-Based Classifier Micro-Engine for Efficient Flow Processing in SDN-Based Internet of Things
In the Internet of things (IoT), network devices and mobile systems should exchange a considerable amount of data with negligible delays. For this purpose, the community has used the software-defined networking (SDN), which has provided high-speed flow-based communication mechanisms. To satisfy the...
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doaj-ffe5c17981ae4c01ab5ee325a2f28e1a2021-07-02T11:04:56ZengHindawi LimitedMobile Information Systems1574-017X1875-905X2020-01-01202010.1155/2020/76410737641073A CRC-Based Classifier Micro-Engine for Efficient Flow Processing in SDN-Based Internet of ThingsMahdi Abbasi0Navid Mousavi1Milad Rafiee2Mohammad R. Khosravi3Varun G. Menon4Department of Computer Engineering, Engineering Faculty, Bu-Ali Sina University, Hamedan 65178-38695, IranDepartment of Computer Engineering, Engineering Faculty, Bu-Ali Sina University, Hamedan 65178-38695, IranDepartment of Computer Engineering, Engineering Faculty, Bu-Ali Sina University, Hamedan 65178-38695, IranDepartment of Computer Engineering, Persian Gulf University, Bushehr, IranDepartment of Computer Science and Engineering, SCMS School of Engineering and Technology, Ernakulam 683582, Kerala, IndiaIn the Internet of things (IoT), network devices and mobile systems should exchange a considerable amount of data with negligible delays. For this purpose, the community has used the software-defined networking (SDN), which has provided high-speed flow-based communication mechanisms. To satisfy the requirements of SDN in the classification of communicated packets, high-throughput packet classification systems are needed. A hardware-based method of Internet packet classification that could be simultaneously high-speed and memory-aware has been proved to be able to fill the gap between the network speed and the processing speed of the systems on the network in traffics higher than 100 Gbps. The current architectures, however, have not been successful in achieving these two goals. This paper proposes the architecture of a processing micro-core for packet classification in high-speed, flow-based network systems. By using the hashing technique, this classifying micro-core fixes the length of the rules field. As a result, with a combination of SRAM and BRAM memory cells and implementation of two ports on Virtex®6 FPGAs, the memory usage of 14.5 bytes per rule and a throughput of 324 Mpps were achieved in our experiments. Also, the performance per memory of the proposed design is the highest as compared to its major counterparts and is able to simultaneously meet the speed and memory-usage criteria.http://dx.doi.org/10.1155/2020/7641073 |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Mahdi Abbasi Navid Mousavi Milad Rafiee Mohammad R. Khosravi Varun G. Menon |
spellingShingle |
Mahdi Abbasi Navid Mousavi Milad Rafiee Mohammad R. Khosravi Varun G. Menon A CRC-Based Classifier Micro-Engine for Efficient Flow Processing in SDN-Based Internet of Things Mobile Information Systems |
author_facet |
Mahdi Abbasi Navid Mousavi Milad Rafiee Mohammad R. Khosravi Varun G. Menon |
author_sort |
Mahdi Abbasi |
title |
A CRC-Based Classifier Micro-Engine for Efficient Flow Processing in SDN-Based Internet of Things |
title_short |
A CRC-Based Classifier Micro-Engine for Efficient Flow Processing in SDN-Based Internet of Things |
title_full |
A CRC-Based Classifier Micro-Engine for Efficient Flow Processing in SDN-Based Internet of Things |
title_fullStr |
A CRC-Based Classifier Micro-Engine for Efficient Flow Processing in SDN-Based Internet of Things |
title_full_unstemmed |
A CRC-Based Classifier Micro-Engine for Efficient Flow Processing in SDN-Based Internet of Things |
title_sort |
crc-based classifier micro-engine for efficient flow processing in sdn-based internet of things |
publisher |
Hindawi Limited |
series |
Mobile Information Systems |
issn |
1574-017X 1875-905X |
publishDate |
2020-01-01 |
description |
In the Internet of things (IoT), network devices and mobile systems should exchange a considerable amount of data with negligible delays. For this purpose, the community has used the software-defined networking (SDN), which has provided high-speed flow-based communication mechanisms. To satisfy the requirements of SDN in the classification of communicated packets, high-throughput packet classification systems are needed. A hardware-based method of Internet packet classification that could be simultaneously high-speed and memory-aware has been proved to be able to fill the gap between the network speed and the processing speed of the systems on the network in traffics higher than 100 Gbps. The current architectures, however, have not been successful in achieving these two goals. This paper proposes the architecture of a processing micro-core for packet classification in high-speed, flow-based network systems. By using the hashing technique, this classifying micro-core fixes the length of the rules field. As a result, with a combination of SRAM and BRAM memory cells and implementation of two ports on Virtex®6 FPGAs, the memory usage of 14.5 bytes per rule and a throughput of 324 Mpps were achieved in our experiments. Also, the performance per memory of the proposed design is the highest as compared to its major counterparts and is able to simultaneously meet the speed and memory-usage criteria. |
url |
http://dx.doi.org/10.1155/2020/7641073 |
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