Hardware Implementations of SVM on FPGA: A State-of-the-Art Review of Current Practice
The Support Vector Machine (SVM) is a common machine learning tool that is widely used because of its high classification accuracy . Implementing SVM for embedded real -time applications is very challenging because of the intensi ve computations required. This in creases the attractiveness of implem...
| Main Authors: | , , |
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| Format: | Others |
| Published: |
International Journal of Innovative Science Engineering and Technology (IJISET),
2017-03-07T03:45:48Z.
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| Subjects: | |
| Online Access: | Get fulltext |
| Summary: | The Support Vector Machine (SVM) is a common machine learning tool that is widely used because of its high classification accuracy . Implementing SVM for embedded real -time applications is very challenging because of the intensi ve computations required. This in creases the attractiveness of implementing SVM on hardware platforms for reaching high performance computing with low cost and power consumption. This paper provides the first comprehensive survey of current literature (2010- 2015) of different hardware implementation s of SVM classifier on Field -Programmable Gate Array (FPGA ). A classification of existing techniques is presented, along with a critical analysis and discussion . A challenging trade -off between meeting embedded real -time systems constraints and high classification accuracy has been observed. Finally , some key future research directions are suggested. |
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| Item Description: | International Journal of Innovative Science, Engineering & Technology, vol.2(11), pp.733 - 752 (20) 2348-7968 |