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01555 am a22002653u 4500 |
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5603 |
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|a dc
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|a Balasubramanian, P
|e author
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|a Dhivyaa, D
|e author
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|a Jayakirthika, JP
|e author
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|a Kaviyarasi, P
|e author
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|a Prasad, K
|e author
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|a Low power self-timed carry lookahead adders
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|b IEEE,
|c 2013-08-13T20:48:53Z.
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|a 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS 2013) held at Ohio State University, Columbus, Ohio, Columbus, Ohio, USA, 2013-08-04to 2013-08-07, pp.457 - 460 (4)
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|a Cell based self-timed synthesis of recursive carry lookahead adders (RCLA) utilizing generate, propagate and kill functions is described in this paper, and are compared with the recently proposed designs of self-timed section-carry based carry lookahead (SCBCLA) adders. From the simulation results corresponding to a 130nm CMOS process, it is found that with 2-bit CLA, the RCLA adder dissipates 20.2% less power than the SCBCLA adder. With 4-bit CLA, the RCLA adder reports power reduction by 16.5% than the SCBCLA adder. Further, for addition widths ranging from 32 to 64-bits, RCLA adders consume 19% less average power compared to SCBCLA adders.
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|a OpenAccess
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|a Self-timed
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|a Quasi-delay-insensitive
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|a Logic synthesis
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|a Standard cells
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|a Carry lookahead
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|a Low power
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|a Conference Contribution
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| 856 |
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|z Get fulltext
|u http://hdl.handle.net/10292/5603
|
