Design of low power integrated CMOS Potentiometric biosensor for direct electronic detection of DNA hybridization

The purpose of this research is to design a low power integrated complementary metal oxide semiconductor (CMOS) detection circuit for charge-modulated field-effect transistor (CMFET) and it is used for the detection of deoxyribonucleic acid (DNA) hybridization. With the available CMOS technology, it...

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Bibliographic Details
Main Authors: Wong, How Hwan (Author), Fan, Vinny Lam Siu (Author), Yusof, Yusmeeraz (Author)
Format: Article
Language:English
Published: Penerbit UTM, 2014.
Subjects:
Online Access:Get fulltext
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100 1 0 |a Wong, How Hwan  |e author 
700 1 0 |a Fan, Vinny Lam Siu  |e author 
700 1 0 |a Yusof, Yusmeeraz  |e author 
245 0 0 |a Design of low power integrated CMOS Potentiometric biosensor for direct electronic detection of DNA hybridization 
260 |b Penerbit UTM,   |c 2014. 
856 |z Get fulltext  |u http://eprints.utm.my/id/eprint/52322/1/WongHowHwan2014_Designoflowpowerintegrated.pdf 
520 |a The purpose of this research is to design a low power integrated complementary metal oxide semiconductor (CMOS) detection circuit for charge-modulated field-effect transistor (CMFET) and it is used for the detection of deoxyribonucleic acid (DNA) hybridization. With the available CMOS technology, it allows the realization of complete systems which integrate the sensing units and transducing elements in the same device. Point-of-care (POC) testing device is a device that allows anyone to operate anywhere and obtain immediate results. One of the important features of POC device is low power consumption because it is normally battery-operated. The power consumption of the proposed integrated CMOS detection circuit requires only 14.87 mW. The detection circuit will amplify the electrical signal that comes from the CMFET to a specified level in order to improve the recording characteristics of the biosensor. Self-cascode topology was used in the drain follower circuit in order to reduce the channel length modulation effect. The proposed detection circuit was designed with 0.18μm Silterra CMOS fabrication process and simulated under Cadence Simulation Tool 
546 |a en 
650 0 4 |a TK Electrical engineering. Electronics Nuclear engineering