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|a XOR and XNOR are popular gates in microprocessors. They are fundamental unit circuits used in adder, multiplexer, comparator, parity checker and generator circuits. This project proposes a new five transistors XOR-XNOR design using FinFET. The use of conventional MOSFET as basic unit of XOR and XNOR design has reached its performance limit due to short channel effects (SCEs) at nanoscale region. International Technology Roadmap for Semiconductors (ITRS) had proposed FinFET to replace conventional MOSFET to overcome the limitations of MOSFET at nanoscale region. Impact of variation FinFET parameters such as gate length, fin height and fin thickness to performance of proposed design are analyzed. In this project, the proposed design is compared with other existing designs in terms of power, delay, power delay product (PDP) and energy delay product (EDP). Simulation results demonstrate the power, delay, PDP and EDP at different supply voltage range from 0.6V to 1.2V using HSPICE alongside with CosmosScope. The simulation results reveal that the proposed design has full output swing with all input combinations. It consumes least power compared to existing designs and has low PDP and EDP. This project also compare the performance between SG FinFET and IG FinFET based designs. IG FinFET based design consumes lesser power but bigger delay. Thus, higher PDP and EDP compared to SG FinFET based design.
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