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|a Design Considerations for Efficient Deep Neural Networks on Processing-in-Memory Accelerators
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|b Institute of Electrical and Electronics Engineers (IEEE),
|c 2021-11-03T14:10:52Z.
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|z Get fulltext
|u https://hdl.handle.net/1721.1/137180
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|a © 2019 IEEE. This paper describes various design considerations for deep neural networks that enable them to operate efficiently and accurately on processing-in-memory accelerators. We highlight important properties of these accelerators and the resulting design considerations using experiments conducted on various state-of-the- art deep neural networks with the large-scale ImageNet dataset.
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|a Article
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|t 10.1109/IEDM19573.2019.8993662
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|t Technical Digest - International Electron Devices Meeting, IEDM
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