A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS

• Main Authors: Kim, Byeong-Su (Contributor), Liu, Yong (Author), Dickson, Timothy O. (Author), Bulzacchelli, John F. (Author), Friedman, Daniel J. (Author)
• Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science (Contributor)
• Format: Article
• Language: English
• Published: Institute of Electrical and Electronics Engineers, 2010-03-18T18:29:47Z.
• Subjects: Article
• Online Access: Get fulltext

 A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is reported. Based on expected channel characteristics, the proposed I/O features low-impedance transmitter termination, high-impedance receiver termination, and a receiver with modified DFE with IIR filter feedback (DFE-IIR). The DFE-IIR receiver uses a single additional IIR filter feedback tap to compensate many post cursors without paying the power and area penalty that would be incurred with a conventional high tap-count DFE. Equalization capabilities of the compact I/O at 10 Gb/s are demonstrated over various channels including conventional chip-to-chip and backplane links with half-baud losses of up to 27 dB. Finally, a transmitter-receiver pair operating over a 40-mm on-chip emulated silicon carrier channel was demonstrated to 8.9 Gb/s, at a link power efficiency of 1.9 mW/Gb/s.