Non-linear operating point statistical analysis for local variations in logic timing at low voltage

• Main Authors: Rithe, Rahulkumar Jagdish (Contributor), Gu, Jie (Author), Wang, Alice (Author), Datla, Satyendra (Author), Gammie, Gordon (Author), Buss, Dennis (Author), Chandrakasan, Anantha P. (Contributor)
• Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science (Contributor)
• Format: Article
• Language: English
• Published: Institute of Electrical and Electronics Engineers (IEEE), 2012-10-19T13:53:03Z.
• Subjects: Article
• Online Access: Get fulltext

For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ¿ 0.5 V), the standard deviation of gate delay becomes comparable to nominal delay, and the Probability Density Function (PDF) of the gate delay is highly non-Gaussian. This paper presents a computationally efficient algorithm for computing the PDF of logic Timing Path (TP) delay, which results from local variations. This approach is called Non-linear Operating Point Analysis for Local Variations (NLOPALV). The approach is implemented using commercial STA tools and integrated into the standard CAD flow using custom scripts. Timing paths from a 28 nm commercial DSP are analyzed using the proposed technique and the performance is observed to be within 5% accuracy compared to SPICE based Monte-Carlo analysis.
Massachusetts Institute of Technology (Presidential Fellowship)