Non-linear operating point statistical analysis for local variations in logic timing at low voltage
For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ¿ 0.5 V), the standard deviation of gate...
| Main Authors: | , , , , , , |
|---|---|
| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
Institute of Electrical and Electronics Engineers (IEEE),
2012-10-19T13:53:03Z.
|
| Subjects: | |
| Online Access: | Get fulltext |