Design issues for interconnection networks in massively parallel processing systems under advanced VLSI and packaging constraints

Bibliographic Details
Main Author:	Lacy, William Stephen
Published:	Georgia Institute of Technology 2007
Subjects:	Pattern recognition systems Parallel processing (Electronic computers) Integrated circuits Very large scale integration
Online Access:	http://hdl.handle.net/1853/14690

id	ndltd-GATECH-oai-smartech.gatech.edu-1853-14690
record_format	oai_dc
spelling	ndltd-GATECH-oai-smartech.gatech.edu-1853-146902013-12-15T03:33:58ZDesign issues for interconnection networks in massively parallel processing systems under advanced VLSI and packaging constraintsLacy, William StephenPattern recognition systemsParallel processing (Electronic computers)Integrated circuits Very large scale integrationGeorgia Institute of Technology2007-05-31T19:22:39Z2007-05-31T19:22:39Z1996-12Dissertationhttp://hdl.handle.net/1853/14690444122Access restricted to authorized Georgia Tech users only.
collection	NDLTD
sources	NDLTD
topic	Pattern recognition systems Parallel processing (Electronic computers) Integrated circuits Very large scale integration
spellingShingle	Pattern recognition systems Parallel processing (Electronic computers) Integrated circuits Very large scale integration Lacy, William Stephen Design issues for interconnection networks in massively parallel processing systems under advanced VLSI and packaging constraints
author	Lacy, William Stephen
author_facet	Lacy, William Stephen
author_sort	Lacy, William Stephen
title	Design issues for interconnection networks in massively parallel processing systems under advanced VLSI and packaging constraints
title_short	Design issues for interconnection networks in massively parallel processing systems under advanced VLSI and packaging constraints
title_full	Design issues for interconnection networks in massively parallel processing systems under advanced VLSI and packaging constraints
title_fullStr	Design issues for interconnection networks in massively parallel processing systems under advanced VLSI and packaging constraints
title_full_unstemmed	Design issues for interconnection networks in massively parallel processing systems under advanced VLSI and packaging constraints
title_sort	design issues for interconnection networks in massively parallel processing systems under advanced vlsi and packaging constraints
publisher	Georgia Institute of Technology
publishDate	2007
url	http://hdl.handle.net/1853/14690
work_keys_str_mv	AT lacywilliamstephen designissuesforinterconnectionnetworksinmassivelyparallelprocessingsystemsunderadvancedvlsiandpackagingconstraints
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Design issues for interconnection networks in massively parallel processing systems under advanced VLSI and packaging constraints

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