Header Parsing Logic in Network Switches Using Fine and Coarse-Grained Dynamic Reconfiguration Strategies
Current ASIC only designs which interface with a general purpose processor are fairly restricted as far as their ability to be upgraded after fabrication. The primary intent of the research documented in this thesis is to determine if the inclusion of FPGAs in existing ASIC designs can be conside...
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ndltd-LACETR-oai-collectionscanada.gc.ca-OWTU.10012-83832014-06-18T03:51:40Z Header Parsing Logic in Network Switches Using Fine and Coarse-Grained Dynamic Reconfiguration Strategies Sonek, Alexander FPGA Coarse Grained Fine Grained Current ASIC only designs which interface with a general purpose processor are fairly restricted as far as their ability to be upgraded after fabrication. The primary intent of the research documented in this thesis is to determine if the inclusion of FPGAs in existing ASIC designs can be considered as an option for alleviating this constraint by analyzing the performance of such a framework as a replacement for the parsing logic in a typical network switch. This thesis also covers an ancilliary goal of the research which is to compare the various methods used to reconfigure modern FPGAs, including the use of self initiated dynamic partial reconfiguration, in regards to the degree in which they interrupt the operation of the device in which an FPGA is embedded. This portion of the research is also conducted in the context of a network switch and focuses on the ability of the network switch to reconfigure itself dynamically when presented with a new type of network traffic. 2014-04-29T19:32:31Z 2014-04-29T19:32:31Z 2014-04-29 2014-04-29 Thesis or Dissertation http://hdl.handle.net/10012/8383 en |
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en |
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FPGA Coarse Grained Fine Grained |
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FPGA Coarse Grained Fine Grained Sonek, Alexander Header Parsing Logic in Network Switches Using Fine and Coarse-Grained Dynamic Reconfiguration Strategies |
description |
Current ASIC only designs which interface with a general purpose processor are fairly restricted as far as their ability to be upgraded after fabrication. The primary intent of the research
documented in this thesis is to determine if the inclusion of FPGAs in existing ASIC designs can be considered as an option for alleviating this constraint by analyzing the performance of
such a framework as a replacement for the parsing logic in a typical network switch.
This thesis also covers an ancilliary goal of the research which is to compare the various methods used to reconfigure modern FPGAs, including the use of self initiated dynamic partial
reconfiguration, in regards to the degree in which they interrupt the operation of the device in which an FPGA is embedded. This portion of the research is also conducted in the context of a
network switch and focuses on the ability of the network switch to reconfigure itself dynamically when presented with a new type of network traffic. |
author |
Sonek, Alexander |
author_facet |
Sonek, Alexander |
author_sort |
Sonek, Alexander |
title |
Header Parsing Logic in Network Switches Using Fine and Coarse-Grained Dynamic Reconfiguration Strategies |
title_short |
Header Parsing Logic in Network Switches Using Fine and Coarse-Grained Dynamic Reconfiguration Strategies |
title_full |
Header Parsing Logic in Network Switches Using Fine and Coarse-Grained Dynamic Reconfiguration Strategies |
title_fullStr |
Header Parsing Logic in Network Switches Using Fine and Coarse-Grained Dynamic Reconfiguration Strategies |
title_full_unstemmed |
Header Parsing Logic in Network Switches Using Fine and Coarse-Grained Dynamic Reconfiguration Strategies |
title_sort |
header parsing logic in network switches using fine and coarse-grained dynamic reconfiguration strategies |
publishDate |
2014 |
url |
http://hdl.handle.net/10012/8383 |
work_keys_str_mv |
AT sonekalexander headerparsinglogicinnetworkswitchesusingfineandcoarsegraineddynamicreconfigurationstrategies |
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1716670419334856704 |