| Summary: | This thesis presents HANP, a network processor architecture designed for high performance Internet protocol processing at layers 2 through 7. The HANP, Highly Adaptive Network Processor, architecture is implemented on FPGA and supports line speeds reaching OC-192. HANP is designed as a platform for the analysis and development of Network Processors. It is intended to serve as a flexible and customizable framework to enable future research on tradeoffs involved in building a Network Processor, including feasibility of FPGA implementation. This thesis outlines the architectural design of the HANP and addresses architectural issues including cache organization, processor optimizations, function distribution and system performance optimizations. Particular attention is given to motivating design choices. FPGA design and implementation issues are also addressed. Detailed analysis of system architecture is performed and comparison of performance results, specifically as they relate to IPv4 Forwarding and Triple-DES De/Encryption performance, show HANP architecture to be a promising solution.
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