| Summary: | Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017. === Cataloged from PDF version of thesis. === Includes bibliographical references (pages 47-49). === The topic covered by this thesis is the project of designing a terahertz imager chip on nowadays commercialized mature silicon platform. In the project, we developed the design method of a multi-functional heterodyne pixel and a scalable array architecture. The pixel is a compact electromagnetic structure simultaneously performs voltage-controlled 140 GHz local oscillation, 280-GHz-signal receiving, sub-harmonic mixing, and intermediate frequency (IF) signal extraction. Each pixel consumes 10 mW power and achieves a sensitivity of 2.9 pW in simulation. The local oscillator (LO) of the pixel is phase coupled with its neighbors; the whole oscillator array is then stabilized by an on-chip THz phase-locked loop. This architecture gives excellent array scalability. First, the LO power is evenly distributed and does not degrade in a larger array scale as a normal centralized array does. Second, the phase noise of the coupled LO network improves linearly with the array size. The simulated phase noise at 1-MHz frequency offset is -90 dBc/Hz for an 8 x 8 array and -101 dBc/Hz for a 32 x 32 array. This chip is capable of digital beam steering, too. The first version of the chip prototype with a 10 x 10 array is fabricated using a 130-nm SiGe BiCMOS process and tested. === by Guo Zhang. === S.M.
|
|---|
