Multi-layer three-dimensional silicon electronics enabled by wafer bonding

Multi-layer three-dimensional silicon electronics enabled by wafer bonding

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006. === Includes bibliographical references (p. 169-179). === Three-dimensional integrated circuits (3-D ICs), in the form of a vertical stack of several interconnected device layers, have...

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Bibliographic Details
Main Author: Tan, Chuan Seng, Ph. D. Massachusetts Institute of Technology
Other Authors: L. Rafael Reif and Anantha P. Chandrakasan.
Format: Others
Language:English
Published: Massachusetts Institute of Technology 2007
Subjects:
Electrical Engineering and Computer Science.
Online Access:http://hdl.handle.net/1721.1/37879

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http://hdl.handle.net/1721.1/37879

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