| Summary: | Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008. === This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. === Includes bibliographical references (p. 155-183). === Over the past two decades, intrinsic MOSFET delay has been scaled commensurate with the scaling of the dimensions. To extend this historical trend in the future, careful analysis of what determines the transistor performance is required. In this work, a new delay metric is first introduced that better captures the interplay of the main technology parameters, and employed to study the historical trends of the performance scaling and to quantify the requirements for the continuous increase of the performance in the future. It is shown that the carrier velocity in the channel has been the main driver for the improved transistor performance with scaling. A roadmapping exercise is presented and it is shown that new channel materials are needed to lever carrier velocity beyond what is achieved with uniaxially strained silicon, along with dramatic reduction in the device parasitics. Such innovations are needed as early as the 32-nm node to avoid the otherwise counter-scaling of the performance. The prospects and limitations of various approaches that are being pursued to increase the carrier velocity and thereby the transistor performance are then explored. After introducing the basics of the transport in nanoscale MOSFETs, the impact of channel material and strain configuration on electron and hole transport are examined. Uniaixal tensile strain in silicon is shown to be very promising to enhance electron transport as long as higher strain levels can be exerted on the device. Calculations and analysis in this work demonstrate that in uniaxially strained silicon, virtual source velocity depends more strongly on the mobility than previously believed and the modulation of the effective mass under uniaxial strain is responsible for this string dependence. === (cont) While III-V semiconductors are seriously limited by their small quantization effective mass, which limits the available inversion charge at a given voltage overdrive, germanium is attractive as it has enhanced transport properties for both electrons and holes. However, to avoid mobility degradation due to carrier confinement as well as L - interband scattering, and to achieve higher ballistic velocity, (111) wafer orientation should be used for Ge NFETs. Further analysis in this work demonstrate that with uniaixally strained Si, hole 3 ballistic velocity enhancement is limited to about 2x, despite the fact that mobility enhancement of about 4x has been demonstrated. Hence, further increase of the strain level does not seem to provide major increase in the device performance. It is also shown that relaxed germanium only marginally improves hole velocity despite the fact that mobility is significantly higher than silicon. Biaxial compressive strain in Ge, although relatively simple to apply, offers only 2x velocity enhancement over relaxed silicon. Only with uniaxial compressive strain, is germanium able to provide significantly higher velocities compared to state-of-the-art silicon MOSFETs. Most recently, germanium has manifested itself as an alternative channel material because of its superior electron and hole mobility compared to silicon. Functional MOS transistors with relatively good electrical characteristics have been demonstrated by several groups on bulk and strained Ge. However, carrier mobility in these devices is still far behind what is theoretically expected from germanium. Very high density of the interface states, especially close to the conduction band is believed to be responsible for poor electrical characteristics of Ge MOSFETs. Nevertheless, a through investigation of the transport in Ge-channel MOSFETs and the correlation between the mobility and trap density has not been undertaken in the past. === (cont) Pulsed I -V and Q-V measurement are performed to characterize near intrinsic transport properties in Ge-channel MOSFETs. Pulsed measurements show that the actual carrier mobility is at least twice what is inferred from DC measurements for Ge NFETs. With phosphorus implantation at the Ge-dielectric interface the difference between DC and pulsed measurements is reduced to about 20%, despite the fact that effects of charge trapping are still visible in these devices. To better understand the dependence of carrier transport on charge trapping, a method to directly measure the inversion charge density by integrating the S/D current is proposed. The density of trapped charges is measured as the difference between the inversion charge density at the beginning and end of pulses applied to the gate. Analysis of temporal variation of trapped charge density reveals that two regimes of fast and slow charge trapping are present. Both mechanisms show a logarithmic dependence on the pulse width, as observed in earlier literature charge-pumping studies of Si MOSFETs with high- dielectrics. The correlation between mobility and density of trapped charges is studied and it is shown that the mobility depends only on the density of fast traps. To our knowledge, this is the first investigation in which the impact of the fast and slow traps on the mobility has been separated. Extrapolation of the mobility-trap relationship to lower densities of trapped charges gives an upper limit on the available mobility with the present gate stack if the density of the fast traps is reduced further. However, this analysis demonstrates that the expected mobility is still far below what is obtained in Si MOSFETs. Further investigations are needed to analyze other mechanisms that might be responsible for poor electron mobility in Ge MOSFETs and thereby optimize the gate stack by suppressing these mechanisms. === by Ali Khakifirooz. === Ph.D.
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